Garrett Stephen Koch

Deterministic self-test of a high-speed embedded memory and logic processor subsystem

A memory built-in self-test state machine (MBIST) was designed to test multiple RAMs, each with differing characteristics with deterministic patterns. These memories are all tested in parallel with a BIST that uses a high-performance pipelined architecture to supply patterns from a single centralized memory BIST state machine at memory cycle speeds. After verifying the RAM integrity, the state machine generates the minimum set of deterministic patterns required to test the associated comparator logic and applies the patterns through the corresponding RAMs to accomplish a 100% stuck fault logic test.

A 370-MHz memory built-in self-test state machine

Hardware and simulation results for a 370 MHz memory built-in self-test state machine are presented. Dynamic differential cascode voltage switch logic, unique clocking techniques, and logic pipelining were used to achieve the 370 MHz performance. Testing of multiple SRAMs and content addressable memories is accomplished with deterministic patterns generated by the state machine. Inclusion of a programmable pattern implemented via scan initialization provides test-pattern flexibility. Failing addresses are stored for redundancy implementation.<<ETX>>