Kenneth R. Elliott

A low power (45mW/latch) static 150GHz CML divider

Operation of a static, current mode logic (CML) frequency divider to clock frequencies exceeding 150GHz is reported. The divide-by-8 circuit described here has been realized in a highly scaled 0.4/spl mu/m InP/InGaAs/InP DHBT technology, dissipates only 45mW per latch, and achieves this using purely resistive loads. Thermal limitations in device performance are observed to play a key role, demonstrating the need for aggressive heat management in high speed technologies. On a full thickness wafer in a 27/spl deg/C ambient, the maximum operating frequency of the divider was 143.6GHz; this range extended to 151.2GHz when an air flow at -30/spl deg/C was established across the wafer.

Heterogeneous wafer-scale integration of 250nm, 300GHz InP DHBTs with a 130nm RF-CMOS technology

The performance advantages of InP based devices over silicon devices are well known, but the ability to fabricate complex, high transistor count ICs is limited both by the relative immaturity of the material system and a limited commercial market. Silicon based devices have made significant advances in device performance, but have not yet matched compound semiconductor device performance. A large commercial market, however, has allowed the silicon system to mature and produce billion transistor count ICs in high volume. It would be advantageous to combine the merits of both of these technologies in order to enable a new class of high performance ICs. This work demonstrates the wafer scale integration of an advanced 250 nm, 300 GHz fT/fMAX InP DHBT technology with IBMs 130 nm RF-CMOS technology (CMRF8SF). Such integration allows the rapid adoption of more advanced CMOS and InP DHBT technology generations.

Highly integrated InP HBT optical receivers

This paper presents two highly integrated receiver circuits fabricated in InP heterojunction bipolar transistor (HBT) technology operating at up to 2.5 and 7.5 Gb/s, respectively. The first IC is a generic digital receiver circuit with CMOS-compatible outputs. It integrates monolithically an automatic-gain-control amplifier, a digital clock and data recovery circuit, and a 1:8 demultiplexer, and consumes an extremely low 340 mW of power at 3.3 V, including output buffers. It can realize a full optical receiver when connected to a photo detector/preamplifier front end. The second circuit is a complete multirate optical receiver application-specific integrated circuit (ASIC) that integrates a photodiode, a transimpedance amplifier, a limiting amplifier, a digital clock and data recovery circuit, a 1:10 demultiplexer, and the asynchronous-transfer-mode-compatible word synchronization logic. It is the most functionally complex InP HBT optoelectronic integrated circuit reported to date. A custom package has also been developed for this ASIC.

Direct digital synthesis for enabling next generation RF systems

Technology advances in HBT (heterojunction bipolar transistor) circuit complexity and device performance are enabling a new generation of circuits for direct synthesis of waveforms in the microwave and sub-mm-wave regions. This improvement in performance will provide the core technology for a new generation of wideband digital systems to support a broad range of defense and commercial applications ranging from software radio, digital communications and advanced RF sensors. Recent results have produced circuits with demonstrated clock rate above 15 GHz with ultimate performance supporting clock rates in excess of 32 GHz.

InP HBT integrated circuit technology with selectively implanted subcollector and regrown device layers

We describe a quasi-planar HBT process using a patterned implanted subcollector with a regrown MBE device layer. Using this process, we have demonstrated discrete SHBT with f/sub t/>250 GHz and DHBT with f/sub t/>230 GHz. The process eliminates the need to trade base resistance for extrinsic base/collector capacitance. Base/collector capacitance was reduced by a factor of 2 over the standard mesa device with a full overlap between the heavily doped base and subcollector regions. The low proportion of extrinsic base/collector capacitance enables further vertical scaling of the collector even in deep submicrometer emitters, thus allowing for higher current density operation. Demonstration ring oscillators fabricated with this process had excellent uniformity and yield with gate delay as low as 7 ps and power dissipation of 6 mW/CML gate. At lower bias current, the power delay product was as low as 20 fJ. To our knowledge, this is the first demonstration of high-performance HBTs and integrated circuits using a patterned implant on InP.

Process and integration technologies for InP ICs

Indium phosphide HBT technology has evolved over the past fifteen years into a versatile technology to demonstrate a variety of very high frequency integrated circuits. This versatility is achieved from several choices of heterostructure epitaxial materials and a variety of semiconductor processes. This paper summarizes the basic material structures and fabrication processes leading to this versatility along with the basic IC fabrication process and enhancements to it. These choices have enabled organizations world-wide to demonstrate not only the fastest ICs in any technology but also low power operation and ICs applicable to OC-768 fiber optic communications and satellite communications along with the military electronics.

Integrated optoelectronic circuits with InP-based HBTs

Integrated optoelectronic circuits that are capable of very high speeds or high functionality have been demonstrated using InP-based heterojunction bipolar transistors (HBTs). Optoelectronic receivers contain photodetectors fabricated from the same epitaxial material structure as the HBTs. High-functionality digital receivers, analog receiver arrays as well as analog-to-digital converters have been realized. Optoelectronic modulation circuits for signal transmission also contain separately grown, surface-coupled multiple- quantum-well (MQW) modulators.

High frequency InAs-channel HEMTs for low power ICs

InAs-channel HEMTs with improved breakdown characteristics were realized by using AlInAs barriers for enhanced hole confinement. A performance of f/sub t/>300 GHz at V/sub ds/ = 0.7 V has been achieved for depletion mode devices. As an important step towards enhancement mode operation, we fabricated devices with charge compensation by p-type doping. Devices with V,= -0.35 V and f/sub t/= 20 GHz were realized. These results, in conjunction with the sub-micron device development, show promise for a low-power highspeed IC technology.

Double heterostructure InP HBT technology for high resolution A/D converters

For high resolution analog circuits we have developed a double heterostructure bipolar transistor (DHBT) technology using InP as the collector material. Our baseline DHBTs have demonstrated current gain /spl beta/, early voltage V/sub A/, f/sub T/, and f/sub max/ of 55, 100 V, 70 GHz, and 60 GHz, respectively. We have implemented an analog cell library to build high resolution /spl Delta//spl Sigma/ modulator circuits in this technology. We have used the cell library to demonstrate a first order modulator and to verify the design of these analog cells. At a sample rate of 4 GSPS and an OSR equal to 32 (i.e., input bandwidth of 62.5 MHz) the first order modulator demonstrated an SNR of 40.3 dB. This first order modulator operates using /spl plusmn/5 V power supplies and dissipates 572 mW.

Dense heterogeneous integration for InP Bi-CMOS technology

InP Bi-CMOS technology capable of wafer-scale device-level heterogeneous integration (HI) of InP HBTs and CMOS has been developed. With this technology, full simultaneous utilization of III–V device speed and CMOS circuit complexity is possible. Simple ICs and test structures have been fabricated, showing no significant CMOS or HBT degradation and high heterogeneous interconnect yield. The heterogeneously integrated differential amplifiers with record performance and HBTs with fT=400GHz were obtained. Thermal vias to the Si substrate provide sufficient heat path to lower HI HBT thermal resistances close to on-InP values. Resulting circuits maintain maximum CMOS integration density and HBT performance, while keeping the heterogeneous interconnect length below 5µm.