Robert J. Webber

Superconductor Digital-RF Receiver Systems

Digital superconductor electronics has been experiencing rapid maturation with the emergence of smaller-scale, lower-cost communications applications which became the major technology drivers. These applications are primarily in the area of wireless communications, radar, and surveillance as well as in imaging and sensor systems. In these areas, the fundamental advantages of superconductivity translate into system benefits through novel Digital-RF architectures with direct digitization of wide band, high frequency radio frequency (RF) signals. At the same time the availability of relatively small 4K cryocoolers has lowered the foremost market barrier for cryogenically-cooled digital electronic systems. Recently, we have achieved a major breakthrough in the development, demonstration, and successful delivery of the cryocooled superconductor digital-RF receivers directly digitizing signals in a broad range from kilohertz to gigahertz. These essentially hybrid-technology systems combine a variety of superconductor and semiconductor technologies packaged with two-stage commercial cryocoolers: cryogenic Nb mixed-signal and digital circuits based on Rapid Single Flux Quantum (RSFQ) technology, room-temperature amplifiers, FPGA processing and control circuitry. The demonstrated cryocooled digital-RF systems are the worlds first and fastest directly digitizing receivers operating with live satellite signals in X-band and performing signal acquisition in HF to L-band at ∼30GHz clock frequencies.

Modular, Multi-Function Digital-RF Receiver Systems

Superconductor digital receiver systems of increasing functionality, modularity and user-friendliness have been developed. The modular design methodology ensures that within its input-output and heat load capacity, the system can be reconfigured to perform a different function by changing the chip module and by reprogramming FPGA-based digital signal processors. One of the systems (ADR-004), originally equipped with a 10 × 10 mm2 channelizing receiver chip for signals intelligence application, was reconfigured with a 5 × 5 mm2 1.1-GHz bandpass ADC chip to perform worlds first multi-net Link-16 demonstration at a U.S. Navy facility. Substantial improvements in system integration have been obtained in each successive generation of digital-RF receiver systems. The latest (third) generation system (ADR-005), hosting a 5 × 5 mm2 7.5-GHz bandpass ADC chip and an FPGA channelizer, successfully repeated the over-the-air SATCOM demonstration performed previously using a 1-cm2 single-chip bandpass digital receiver with an on-chip superconductor channelizer. This system ran error-free for over 12 hours with and without a low-noise amplifier. To our knowledge, this is the first time an X-band SATCOM receiver has been operated without analog amplification and down-conversion in a military application.

Cryocooled wideband digital channelizing radio-frequency receiver based on low-pass ADC

We have demonstrated a digital receiver performing direct digitization of radio-frequency signals over a wide frequency range from kilohertz to gigahertz. The complete system, consisting of a cryopackaged superconductor all-digital receiver (ADR) chip followed by room-temperature interface electronics and a field programmable gate array (FPGA) based post-processing module, has been developed. The ADR chip comprises a low-pass analog-to-digital converter (ADC) delta modulator with phase modulation–demodulation architecture together with digital in-phase and quadrature mixer and a pair of digital decimation filters. The chip is fabricated using a 4. 5k A cm −2 process and is cryopackaged using a commercial-off-the-shelf cryocooler. Experimental results in HF, VHF, UHF and L bands and their analysis, proving consistent operation of the cryopackaged ADR chip up to 24.32 GHz clock frequency, are presented and discussed.

Integration of cryocooled superconducting analog-to-digital converter and SiGe output amplifier

HYPRES is developing a prototype digital system comprising a Nb RSFQ analog-to-digital converter (ADC) and SiGe amplifiers on a commercial two-stage cryocooler. This involves the detailed thermal, electrical, and mechanical design of the ADC chip mount, input/output (I/O) cables, and electromagnetic shielding. Our objective is to minimize the heat load on the second (4 K) stage of the cryocooler, in order to ensure stable ADC operation. The design incorporates thermal radiation shields and magnetic shielding for the RSFQ circuit. For the I/O cables, the thermal design must be balanced against the acceptable attenuation of RF lines and resistance of DC bias lines. SiGe heterojunction bipolar transistor (HBT) signal conditioning circuits, placed on the first (60 K) stage of the cryocooler, will amplify the mV-level ADC outputs to V-level (e.g., ECL) outputs for seamless transition to room-temperature electronics. Cooling these HBT circuits lowers noise and improves their high-frequency performance. Demonstration of this prototype should lead the way to commercialization of high-speed digital superconducting systems, for such applications as wireless communication, radars, and switching networks.

Effects of superconducting return currents on RSFQ circuit performance

Complex RSFQ circuits are typically dc-biased with one or more current bias trees, with current returning through a superconducting ground plane. As the bias currents become larger in more complex circuits, it is increasingly critical to pay attention to the distribution of these return currents, and the effects of the resulting magnetic fields on the performance of the RSFQ circuits. We have modeled the current and field distributions, and found that magnetic field and flux are indeed significant. This has been confirmed by direct measurement using a distribution of SQUIDs. Furthermore, we have measured the performance of several RSFQ circuits, and have found that currents in the ground plane can significantly affect performance margins. Approaches to circuit and system designs that can reduce these problems are discussed.

Current Leads and Optimized Thermal Packaging for Superconducting Systems on Multistage Cryocoolers

Packaging of a superconducting electronic system on a compact multistage cryocooler requires careful management of thermal loads from input and output leads, in order not to exceed the heat lift capacity of the various stages of the cooler. In particular, RSFQ systems typically require a large total bias current or greater. A general analysis of resistive wires shows that the tradeoff between heat flow and Joule heating yields a minimum heat load from optimized bias leads on a low- stage, given by , where is the thermalization temperature of the leads on the previous (hotter) stage. This is independent of the material, number, and geometry of the leads, as long as the total lead resistance is optimized. A similar tradeoff between heat flow and signal attenuation can be applied to the optimization of high-frequency input/output lines. Superconducting leads are not subject to these limitations, and can result in further reduction in heat load. Design examples are presented for an RSFQ-based radio receiver on either a two-stage or a four-stage cooler.

Ultra-Low Heat Leak YBCO Superconducting Leads for Cryoelectronic Applications

We report on high temperature superconductor (HTS) DC current leads developed for the specific purpose of delivering small currents (<100 mA) to cryocooled electronic devices operating at 4 K, with significantly reduced heat leak. Multi-stage cryocoolers can provide a suitable platform for niobium-based superconducting electronics at 4 K; the necessary multiple parallel biasing of the circuitry can result in total currents of several amps, which can produce substantial thermal loading of the cryocooler when conventional resistive leads are used. Our approach has been to adapt the comparatively mature technology of high-current second-generation (2G) YBCO-coated conductor tape to low current needs by splitting the tape into electrically isolated narrow lines by ion milling. Performance issues discussed are: obtained critical currents, thermal conductance of the composite conductors, line-to-line electrical isolation, resistance of the joints and robustness. Operation as a current lead between the first and second stage of a Gifford-McMahon cryocooler is reported.

Progress in the Development of Cryocooled Digital Channelizing RF Receivers

HYPRES is developing a class of digital receivers featuring direct digitization at radio frequency. The complete system, consisting of a cryopackaged Nb superconductor all-digital receiver (ADR) chip followed by room-temperature interface electronics and a field-programmable gate array (FPGA) based post-processing module, has been developed. Depending on the targeted application the ADR chip comprised either a low-pass delta with phase modulation-demodulation architecture or X-band band-pass sigma-delta modulators together with digital in-phase and quadrature mixer and a pair of digital decimation filters. The chips were fabricated using a 4.5-kA/cm2 HYPRES process and were cryopackaged using a commercial-off-the-shelf cryocooler. Recently, with significant improvements in chip cryopackage, room-temperature electronics and FPGA programming we were able to achieve stable operation of a low-pass ADR at 28.16 GHz and X-band ADR at 30.72 GHz clock frequencies. Experimental results are presented and discussed.

4 K cryocooler implementation of a DC programmable voltage standard

NIST and HYPRES, Inc. have been collaborating to develop a 1 Volt DC programmable Josephson voltage standard (PJVS) that operates on a closed-cycle refrigerator. The goal of this work is to construct a platform that will allow the chip to work at 4 K without liquid helium, thereby making the system more convenient and eliminating the need for users to handle liquid cryogens. In our existing PJVS systems, the Josephson chip temperature is the only parameter that is not computer controlled. The addition of a cryocooler will allow automated warming and cooling of the Josephson device and enable an intrinsic voltage standard system in which every control function is automated, and the only required user input is the desired output voltage. The cryocooler package is designed to allow PJVS chips to be easily interchanged between the cryocooler and liquid helium cryoprobes.

Integration of a 4-Stage 4 K Pulse Tube Cryocooler Prototype With a Superconducting Integrated Circuit

A custom-designed laboratory prototype of a four-stage Stirling-type pulse tube cryocooler was recently developed by Lockheed Martin for niobium integrated circuits (ICs) operating close to 4 K. Basic system performance has been verified by integration with a Nb IC test chip, with cells that include a high-speed rapid single flux quantum (RSFQ) binary counter. For 650 W total compressor power, extended stable operation of the counter at T=4.5 K was demonstrated with a clock frequency up to 46 GHz, with 25 mW of excess cooling capacity on the coldest stage. The thermodynamic, electromagnetic, and mechanical performance are promising for the development of an improved compact cryocooler for practical superconducting electronic applications in fields such as wireless communications.