Robert Pasko

A new algorithm for elimination of common subexpressions

The problem of an efficient hardware implementation of multiplications with one or more constants is encountered in many different digital signal-processing areas, such as image processing or digital filter optimization. In a more general form, this is a problem of common subexpression elimination, and as such it also occurs in compiler optimization and many high-level synthesis tasks. An efficient solution of this problem can yield significant improvements in important design parameters like implementation area or power consumption. In this paper, a new solution of the multiple constant multiplication problem based on the common subexpression elimination technique is presented. The performance of our method is demonstrated primarily on a finite-duration impulse response filter design. The idea is to implement a set of constant multiplications as a set of add-shift operations and to optimize these with respect to the common subexpressions afterwards. We show that the number of add/subtract operations can be reduced significantly this way. The applicability of the presented algorithm to the different high-level synthesis tasks is also indicated. Benchmarks demonstrating the algorithms efficiency are included as well.

Optimization method for broadband modem FIR filter design using common subexpression elimination

An approach for broadband modem FIR filter design optimization is presented. It addresses the minimization of the number of adder-subtractors used in the hardware implementation of a FIR filter (the multiple constant multiplication problem). The method is based on the identification and elimination of common n-bit pattern subexpressions in a set of filter coefficients by means of an exhaustive search. We give an algorithm description of our solution and demonstrate its performance on selected examples. A comparison of the results obtained by other authors is made, and finally, optimization and synthesis results on a realistic example-a 64-tap root-raised-cosine filter with 10-bit CSD (canonical signed digit) coefficients-are given.

Design of Cam-E-leon, a run-time reconfigurable web camera

This paper describes the design of a reconfigurable Internet camera, Cam-E-leon, combining reconfigurable hardware and embedded software. The software is based on the µClinux operating system. The network appliance implements a secure VPN (Virtual Private Network) with 3DES encryption and Internet camera server (including JPEG compression). The appliances hardware can be reconfigured at run-time by the client, thus allowing to switch between several available image manipulation functions. The reconfiguration information is retrieved from a reconfiguration server on the network, thus allowing a flexible implementation of new services.The paper describes the hardware and software architecture of the platform, the run-time reconfiguration features of the platform including the integration of the platform in the network, and the design process followed to implement the appliance starting from a high-level executable specification.

Techniques to Evolve a C++ Based System Design Language

Complex systems-on-chip present one of the most challenging design problems. To meet this challenge, new design languages capable of modelling such heterogeneous, dynamic systems are needed. For implementation of such a language, the use of an object oriented C++ class library has proven to be a promising approach, since new classes dealing with design- and platform-specific problems can be added in a conceptual and seamlessly reusable way. This paper shows the development of such an extension aimed to provide a platform-independent high-level structured storage object through hiding of the low-level implementation details. It results in a completely virtualised, user-extendible component, suitable for use in heterogeneous systems.

High-level data-access analysis for characterisation of (sub)task-level parallelism on Java

In the era of future embedded systems the designer is confronted with multi-processor systems both for performance and energy reasons. Exploiting (sub)task-level parallelism is becoming crucial because the instruction-level parallelism alone is insufficient. The challenge is to build compiler tools that support the exploration of the task-level parallelism in the programs. To achieve this goal, we have designed an analysis framework to evaluate the potential parallelism from sequential object-oriented programs. Parallel-performance and data-access analysis are the crucial techniques for estimation of the transformation effects. We have implemented support for platform-independent data-access analysis and profiling of Java programs, which is an extension to our earlier parallel-performance analysis framework. The toolkit comprises automated design-time analysis for performance and data-access characterisation, program instrumentation, program-profiling support and post-processing analysis. We demonstrate the usability of our approach on a number of realistic Java applications.

Functional verification of an embedded network component by co-simulation with a real network

In this paper, we propose a technique for verification of the functionality of a hardware networking component by including an existing real-world network into the simulation loop. As a consequence, there is no need for a high-level network model to create the system simulation. Instead, third party hardware/software can be used for the crosschecking of the designs functionality. The technique is most suitable for C/C++ based design methodologies which can directly access the operating system (OS) network interface functions. Because of that, the integration of a real network into the simulation loop can be straightforward. We demonstrate the method on verification of a Hypertext Transfer Protocol (HTTP) hardware implementation used in a design of an embedded web-camera with direct Internet connectivity.

Design of a secure, intelligent, and reconfigurable Web cam using a C based system design flow

This paper describes the design of a reconfigurable Internet camera, Cam-E-leon, combining reconfigurable hardware and embedded software. The software is based on the /spl mu/Clinux operating system. The network appliance implements a secure VPN (virtual private network) with 3DES encryption and Internet camera server (including JPEG compression). The appliances hardware can be reconfigured at run-time by the client, thus allowing us to switch between several available image manipulation functions. This paper focuses on the design process used to implement the appliance starting from a high-level executable specification.

Performance Analysis for Identification of (Sub-)Task-Level Parallelism in Java

In the era of future embedded systems the designer is confronted with multiple processors both for performance and energy reasons. Exploiting (sub-)task-level parallelism is crucial when targeting those multi-processor systems, because ILP on itself is not sufficient.

Platform design approach for re-configurable network appliances

The presented platform-based object-oriented modeling concept for system design allowed us to create a networked hardware reconfigurable camera in a 25 man-month schedule with concurrent development of application and target FPGA platform. The developed TCP/IP layer achieves throughput of 2 Mb/s/MHz and the complete application logic consumes 700 mW at 20 MHz.