Luc Rijnders

A methodology and design environment for DSP ASIC fixed point refinement

Complex signal processing algorithms are specified in floating point precision. When their hardware implementation requires fixed point precision, type refinement is needed. The paper presents a methodology and design environment for this quantization process. The method uses independent strategies for fixing MSB and LSB weights of fixed point signals. It enables short design cycles by combining the strengths of both analytical and simulation based methods.

A programming environment for the design of complex high speed ASICs

A C++ based programming environment for the design of complex high speed ASICs is presented. The design of a 75 Kgate DECT transceiver is used as a driver example. Compact descriptions, combined with efficient simulation and synthesis strategies are essential for the design of such a complex system. It is shown how a C++ programming approach outperforms traditional HDL-based methods.

Synthesis of multi-rate and variable rate circuits for high speed telecommunications applications

A design methodology for the synthesis of digital circuits used in high throughput digital modems is presented. The methodology spans digital modern design from the link level to the gate level. The methodology uses a C++-based untimed dataflow system description, which is gradually refined to an optimized, bit-true and clock cycle true C++-description. Through this refinement, a bridge from link level design semantics to architectural VHDL semantics is made within one and the same environment.

Performance Analysis for Identification of (Sub-)Task-Level Parallelism in Java

In the era of future embedded systems the designer is confronted with multiple processors both for performance and energy reasons. Exploiting (sub-)task-level parallelism is crucial when targeting those multi-processor systems, because ILP on itself is not sufficient.

System Level Architecture Exploration for Reconfigurable Systems On Chip

During the last years, a new type of systems-on-chip called, reconfigurable systems-on-chip (RSoCs), has appeared. The design of such systems is a complex task and requires innovative methods to support the development process. In this paper, the authors present two alternative approaches for the efficient architecture exploration of RSoCs, based on SystemC language and on OCAPI-xl environment. The approaches introduced, allow early evaluation of alternative mappings of systems functionality onto different architectures. As a result, the time consuming iterations from lower design stages are eliminated and reduced design time is achieved. The paper proves the effectiveness of the proposed approaches through three different case studies, borrowed from complementary domains