Robert Wieland

Through silicon via technology — processes and reliability for wafer-level 3D system integration

3D integration is a rapidly growing topic in the semiconductor industry that encompasses different types of technologies. The paper addresses one of the most promising technologies which uses through silicon vias (TSV) for interconnecting stacked devices on wafer-level to perform high density interconnects with a good electrical performance at the smallest form factor for 3D architectures. Fraunhofer IZM developed a post frontend 3D integration process, the so- called ICV-SLID technology based on metal bonding using solid-liquid-interdiffusion (SLID) soldering. The SLID metal system provides the mechanical and the electrical connection, both in one single step. The ICV-SLID fabrication process is well suited for the cost-effective production of both, high- performance applications (e.g. 3D microprocessor) and highly miniaturized multi-functional systems. The latter preferably in combination with wafer-level die stacking, as e.g. Thin Chip Integration (TCI) or SnAg-microbump technologies. The fabrication of distributed wireless sensor systems (e. g. e-CUBESreg) is a typical example for the need of such mixed approaches.

Vertical System Integration by Using Inter-Chip Vias and Solid-Liquid Interdiffusion Bonding

A new approach for 3D system integration, called Inter Chip Via-Solid Liquid Interdiffusion (ICV-SLID) is introduced. This is a new chip-to-wafer stacking technology which combines the advantages of the Inter Chip Via (ICV) process and the solid-liquid-interdiffusion technique (SLID) of copper and tin. The fully modular ICV-SLID concept allows the formation of multiple device stacks. A test chip was designed and the total process sequence of the ICV-SLID technology for the realization of a three-layer chip-to-wafer stack was demonstrated. The proposed wafer-level 3D integration concept has the potential for low cost fabrication of multi-layer high-performance 3D-SoCs and is well suited as a replacement for embedded technologies based on monolithic integration.

TSV based silicon interposer technology for wafer level fabrication of 3D SiP modules

Silicon interposers with through silicon vias (TSVs) have become important key components of 3D architectures. They are used as intermediate carrier and wiring device for IC components like logics, memories and sensors. Due to custom specific front and back side wiring interposers enable to adapt the fine pitch IO terminals of the mounted ICs to the IO geometries of the package level. High density copper filled TSVs with high aspect ratio as well as high density multi layer wiring using electro plated copper as conductive material and low loss dielectrics enable high performance signal transmission at interposer level without serious losses by parasitic effects. This paper presents the fabrication steps for wafer level processing of silicon interposers with copper filled TSVs as well as their wafer level assembly with IC components. Special focus is drawn on the TSV formation process including via etching, isolation and filling as well as front side high density wiring and subsequent backside processing of the thin TSV wafers. In this context, also temporary wafer to wafer bonding which is required for backside processing of thin TSV wafers is discussed. The final interposers which carry one or more IC components have lateral dimensions up to several square centimeters and thicknesses between 50–100 μm. They include up to several thousands of TSVs per device with a single electrical resistance between 4.9–5.7 mOhms. All processes were run using production equipment at 200 mm wafers.

3D image sensor SiP with TSV silicon interposer

3D system integration is a fast growing field that encompasses different types of technologies. [1] The technology chosen for a specific application will be selected according to the required electrical performance of the systems, the footprint, cost and time to market. Other important factors are the boundary conditions given for the specific components e.g. die size, integration compatibility, component availability (wafer vs. bare die) and testability. The paper discusses a specific 3D image sensor system for automotive applications. The system is based on wafer level technology using silicon interposer with Through Silicon Vias (TSVs), a flip chip assembled sensor element and a microcontroller. The specific system concept, the technical solution and results are discussed.

3D System Integration

3D-integration is a promising technology towards higher interconnect densities and shorter wiring lengths between multiple chip stacks, thus achieving a very high performance level combined with low power consumption. This technology also offers the possibility to build up systems with high complexity just by combining devices of different technologies. For ultra thin silicon is the base of this integration technology, the fundamental concepts will be described, as well as appropriate handling concepts.

3D-integration of silicon devices: a key technology for sophisticated products

3D integration is a key solution to the predicted performance increase of future electronic systems. It offers extreme miniaturization and fabrication of More than Moore products. This can be accomplished by the combination of Through-Silicon-Via (TSV) technologies for shortened electrical signal lines and Solid Liquid Interdiffusion (SLID) for highly reliable assembly. Depending on the chosen technology concept, TSVs are filled with either tungsten or copper metal. Thinning of silicon as part of the process flow enables devices as thin as 30 µm, so multilayer stacking will result in ultra-thin systems. All these 3D integration concepts focus on wafer level processing to achieve the highest miniaturization degree and highest processing reliability as well as enabling high volume cost-effective fabrication.

Silicon-interposer with high density Cu-filled TSVs

A silicon-interposer technology with high density Cu-filled TSVs and Cu-based redistribution layers was realized. Test structures in a process control module were used for electrical characterization.

3D System Integration for high density Interconnects

3D-Integration is a promising technology towards higher interconnect densities and shorter wiring lengths between multiple chip stacks, thus achieving a very high performance level combined with low power consumption. This technology also offers the possibility to build up systems with high complexity by combining devices of different technologies. The fundamental processing steps will be described, as well as appropriate handling concepts and first electrical results of realized 3D-integrated stacks.

Application of the SLID-ICV interconnection technology for the ATLAS pixel upgrade at SLHC

The presented R&D activity is focused on the development of a new detector for the upgrade of the ATLAS pixel system at SLHC at CERN, Geneva, employing thin pixel sensors together with a novel vertical integration technology. It consists of the Solid-Liquid-InterDiffusion (SLID) interconnection, which is an alternative to the standard solder bump-bonding, and Inter Chip Vias (ICV) for routing the signal vertically through the readout chips. The SLID interconnection is characterized by a very thin eutectic Cu-Sn alloy, achieved through the deposition of 5 μm of Cu on both sides, and 3 μm of Sn on one side only. The thin pixels are connected by the SLID process to the read out ASICs in the “chip to wafer” approach using tested known good dies. The inter chip vias are placed in the r/o chips before the SLID process in the “via last” approach. This approach gives the highest flexibility for the choice of the sensor and ASIC technology. The best possible sensors can be produced in a highly specialized technology on a dedicated process line and then in subsequent post-processing bonded to r/o ASICs coming from a standard CMOS line.

Superior etch performance of Ar/N 2 /F 2 for PECVD chamber clean

F<inf>2</inf> gas mixtures offer ideal properties to be employed as chamber cleaning gas: low dissociation energy and high reactivity, which leads to superior efficiency and ease of abatement. In this work, a new F<inf>2</inf> gas mixture was used with a combination ratio of 10% Ar, 20% F<inf>2</inf> and 70% N<inf>2</inf> in order to obtain a maximum of 20% fluorine in inert gases. This novel Ar/N<inf>2</inf>/F<inf>2</inf> gas mixture has been evaluated as a candidate to replace conventional cleaning gases, like NF<inf>3</inf>, C<inf>2</inf>F<inf>6</inf> and CF<inf>4</inf> in an industrial AMAT P5000 CVD chamber tool. Standard equipment has been used, showing complete compatibility with the new gas. The tested Ar/N<inf>2</inf>/F<inf>2</inf> mixture shows improvements in both parameters, cleaning at a faster rate (up to more 27%), even requiring a lower amount of gas (minus 96% versus NF<inf>3</inf>). The higher etching rate and the lower gas consumption assure a sensible CoO (Cost of Ownership) advantage to any potential user. The superior etch rate performance of the Ar/N<inf>2</inf>/F<inf>2</inf> gas mixture was combined with excellent etch non uniformities values, of °3% (1sigma) on SiO<inf>2</inf> and of °8% (1sigma) on Si<inf>3</inf>N<inf>4</inf>, respectively. Also amorphous Silicon (a-Si) was etched completely and uniformly. The particle performance data showing in average just 14 particle adders (0.25µm), indicating that no significant particle contamination was induced by the process and Ar/N<inf>2</inf>/F<inf>2</inf> can be used as a highly clean and efficient etching gas as well as an ideal drop-in replacement for the conventional cleaning gases.