Roberto d'Amore

A low-cost FPGA implementation of the Advanced Encryption Standard algorithm

This work presents an architecture for a hardware implementation of the Rijndael block cipher with 128-bit key. Rijndael block cipher was recently adopted by the United States government as the new Advanced Encryption Standard (AES). The proposed architecture was designed for low-cost, mid-density FPGA.

Using FPGAs to implement asynchronous pipelines

The asynchronous paradigm has interesting features due to the lack of the clock signal and it is another option for the project of digital systems. This paradigm has several design styles, where the micropipeline style is the most suitable one for FPGA platforms, due to the simplicity of its control. In this paper, we propose a pipeline architecture to implement asynchronous digital systems, in bundled-data micropipeline style, considering FPGAs as target devices. Through a case study, we show that the proposed architecture presents a 29% decrease in latency time and a 13% increase in throughput, compared with the state of the art architecture MOUSETRAP.

A low complexity image compression solution for onboard space applications

In this work, a real time hardware data compression solution for raster scan cameras, to be onboard the next generation of Remote Sensing Brazilian satellites, is proposed. The options for image data compression methods are briefly covered to substantiate the choice: a low complexity implementation based on JPEG-LS, near-lossless compression algorithm, which can be synthesized in a single electronic device. JPEG-LS performance in terms of compression rates and loss is evaluated by processing remote sensing rough images through in-house developed software tool. Finally, the description and results of an implementation in FPGA are presented and compared to other works, emphasizing the differences related to application requirements.

Impact evaluation of logic blocks configuration on FPGA's soft error rate estimation

The Soft Error Rate (SER) of an electronic system depends on its sensitivity to the transient faults on its internal elements. Therefore, the SER is commonly estimated by injecting faults into these elements, using a uniform fault distribution. Although this approach can adequately support a feasibility or a compliance analysis, a more accurate estimation would offer a suitable parameter for classifying and choosing an optimum system design. The SER estimation accuracy could be improved by using the fault probability of each internal element. This approach would be especially interesting for FPGAs, which have Configurable Logic Blocks (CLBs) implementing different functions with distinct fault probabilities. In this context, this work evaluates how the CLB configuration impacts the SER estimation of two circuits implemented on a ProASIC3E FPGA. A difference of 14% is observed between the SER estimation considering the CLBs individual fault probabilities and the SER estimation with uniformly distributed faults. Additionally, the SER considering the CLB configuration is closer to the estimation obtained from a transistor-level fault injection. This result shows the influence of the CLB configuration on the SER estimation and indicates that a more accurate value can be obtained by taking this factor into account.

FPGA implementation of optimized XBM specifications by transformation for AFSMs

The asynchronous paradigm is an alternative to digital system design because it eliminates the problems related to the clock signal, such as clock skew, clock distribution and power dissipation of the clock. An interesting style for asynchronous design, which is familiar to designers, divides the system in an asynchronous controller with synchronous datapath. A specification known as Extended Burst-Mode (XBM) is the most adequate one to describe the asynchronous controllers in this design style. The XBM specification must meet a number of properties to be implementable. A property known as the signal polarity may affect the controller performance. To satisfy the signal polarity, the designer must often introduce some state transitions that do not perform any operation, which are called in this paper as “dead transitions”. An XBM specification with dead transitions can reduce the controller performance. In this paper, we propose an algorithm that eliminates dead transitions in a XBM specification. This elimination occurs by transforming the original XBM specification, which leads to an optimization of the system performance. The algorithm was applied to seven well-known benchmarks and obtained a reduction of up to 37% in processing time.

Proposal of hardware-in-the-loop control platform for small fixed-wing UAVs

Unmanned Aerial Vehicles (UAVs) have received considerable attention from the academic community and technology solutions companies, given their civilian and military applications. The autopilot system shall be thoroughly tested in lab because an accident may cause irreversible damage to the UAV. This article presents a proposal of a Hardware-In-the-Loop platform for testing and validation of a small fixed-wing aircraft. Besides a communication system, it was developed a deflection measurement platform of the aircraft control surfaces. This measurement platform was validated, enabling future work on implementing embedded control algorithms.

Design of a high-sensitivity sub-40µg capacitive accelerometer using a Multi-Project Wafer process

This paper presents the design of a high-sensitivity parallel plates accelerometer intended to inertial navigation. Common issues of the parallel plates topology have been addressed to improve the sensor capacitive sensitivity and resolution. A sensitivity of 350 pF/g and a sub-40μg/sqHz resolution have been achieved through simulation. As this sensor will be operated in closed-loop mode with electrostatic force feedback, the small displacements between plates allow the use of low voltages in the feedback loop. The device is being fabricated under a Multi-Project Wafer program; the use of a limited fabrication process added several difficulties in the design process.