Francesco Brandonisio

An all-digital PLL with a first order noise shaping Time-to-Digital Converter

This paper presents an All Digital PLL (ADPLL) based on a first order noise shaping Time-to-Digital Converter (TDC). The architectures of two state-of-art ADPLLs and a state-of-art Gated Ring Oscillator (GRO) TDC are described. The architecture of the GRO TDC is compared with that of the proposed Local Oscillator based TDC (LO TDC) in terms of spectral performance. Behavioral Verilog-AMS models of the LO, exact LO, and exact GRO TDCs are described briefly. Finally, the Verilog-AMS models of three ADPLLs, including the TDC models, are compared by means of simulations.

Comparison of ring and LC oscillator-based ILFDs in terms of phase noise, locking range, power consumption and quality factor

In this paper, we compare a 2GHz LC oscillatorbased ILFD with a 2GHz ring oscillator-based ILFD in terms of locking range, phase noise and power consumption. We recall the definitions of open and closed loop quality factor. The open loop quality factor is convenient for relating phase noise to the circuit parameters. The closed loop quality factor is suitable for relating locking range and circuit parameters. By means of simulations, the locking range and phase noise are determined for different values of quality factor and power consumption. We show qualitatively how to tune the circuit parameters to achieve better performance.

First Order Noise Shaping Local-Oscillator Based Time-to-Digital Converter

This paper presents a First Order Noise Shaping Local-Oscillator Based Time-to-Digital Converter (LO TDC). The architecture and governing equations of the LO TDC are described. In order to show the effect of noise shaping on the resolution of the TDC, the system “LO TDC plus moving average filter” is introduced. An equation to predict the resolution of the system “LO TDC plus filter” is given. Then, the Matlab model of the system “LO TDC plus filter” is illustrated briefly, and some example of simulated input-output characteristics are shown. Afterwards, the implementation of the LO TDC on an FPGA is described. A comparison between the predicted, simulated and measured values of the resolution of the system “LO TDC plus filter” is reported. Finally, we show spectra of the output signals of the LO TDC from experiments and simulations.

Advantages of Noise Shaping and Dither

We have shown in Chap. 3 that zeroth and first-order noise-shaping TDCs can be modelled by quantizers and first-order sigma-delta modulators, respectively. In this chapter, we consider the cases in which a dither signal \({\textit{dtr}}[n]\) is added to the input \(in[n]\) of a quantizer or a sigma-delta modulator followed by a moving average filter. In order to keep our analysis simple, we assume that \(\textit{dtr}[n]\) is uniformly distributed over the interval \([-\varDelta d/2, \varDelta d/2]\). Dither has the effect of making the quantization errors that are associated with the quantizer and the sigma-delta modulator more white and uniformly distributed over their intervals of definition. The moving average filters remove part of the noise associated with the dither and the quantization error. The removal of part of the power of the quantization error corresponds to an increase in the effective precision of a quantizer or a sigma-delta modulator when followed by a moving average filter. We determine analytically the precisions of these systems in terms of the maximum difference between the input and the output when this difference is bounded. In the cases where the maximum difference between the input and output is unbounded (because its distribution is Gaussian, for example), we assume that a measure of the precision of a quantizer or a sigma–delta modulator is the size of the interval \([-3\sigma , 3\sigma ]\) of the contributions of the quantization error and the dither to the output, where \(\sigma \) is the standard deviation.

Modelling and Estimating Phase Noise with Matlab

The goal of this chapter is to illustrate how to model and estimate the phase noise of a sampled signal using Matlab. We first illustrate how the phase noise of a signal is related to the phase deviations of the signal. We then show how to model the phase noise of a noisy signal using Matlab.

Analytical Predictions of Phase Noise in ADPLLs

In this chapter, we will derive analytical predictions of the phase noise in TDC-based and accumulator-based ADPLLs with \(l\)th-order noise shaping TDCs and DCO driven by a sigma-delta modulator.

Phase Digitization in All-Digital PLLs

In this chapter, we review the operating principles of the main topologies of ADPLLs (PFD-plus-TDC-based, TDC-based and accumulator-based ADPLLs) in terms of the integer and fractional parts of the phase difference. We also mention the flip-flop-based ADPLL which can be considered as a particular case of a TDC-based ADPLL. We show models that describe the phase-to-digital conversion in each ADPLL architecture when the integer part of the phase difference is equal to or different from zero. We show that a flip-flop based ADPLL can be viewed as the ADPLL architecture with the simplest phase-to-digital conversion. We also discuss possible strategies to clock the digital filter in the various ADPLL architectures. We show how to modify the ADPLL architectures to synthesize a fractional ratio between the frequencies of the reference oscillator and the DCO. Finally, we compare the ADPLL architectures in terms of phase-to-digital conversion, TDC dynamic range, and metastability.

Efficient Modeling and Simulation of Accumulator-Based ADPLLs

In this chapter, we focus on the behavioral modeling and simulation of accumulator-based ADPLLs. First, we introduce some basic concepts related to mixed-signal systems and simulators. We highlight the major issues for the simulation of an ADPLL as an example mixed-signal system.

A Unifying Framework for TDC Architectures

A TDC is an analog-to-digital converter that converts the duration of a time interval to a digital word [1].

Implementation of a pulse-holding Time-to-Digital Converter on an FPGA

In this work, we describe the implementation of a pulse-holding Time-to-Digital Converter (TDC) on a Xilinx Spartan 6 FPGA. We describe the operation of a pulse-holding TDC and we compare it with that of a pulse-shrinking TDC, which is the most similar TDC in the literature. We then illustrate a Simulink model of a pulse-holding TDC and the TDC that was implemented on a FPGA. The pulse-holding TDC uses a moving average filter to remove the quantization noise and improve the precision of the measurements. We show from simulations and experiments that the maximum modulus of the difference between the the input and output of the TDC can be reduced from 2 ns to less than 70 ps by means of a moving average filter.