Roger J. Stierman

Kirkendall void formation in eutectic SnPb solder joints on bare Cu and its effect on joint reliability

The electronic packaging industry has been using electroless Ni(P)∕immersion Au as bonding pads for solder joints. Because of the persistence of the black pad defect, which is due to cracks in the pad surface, the industry is looking for a replacement of the Ni(P) plating. Several Cu-based candidates have been suggested, but most of them will lead to the direct contact of solder with Cu in soldering. The fast reaction of solder with Cu, especially during solid state aging, may be a concern for the solder joint reliability if the package will be used in a high temperature environment and is highly stressed. In this work, the reaction of eutectic SnPb solder with electrodeposited laminate Cu is studied. Emphasis is given to the evolution of the microstructure in the interfacial region during solid state aging and its effect on solder joint reliability. A large number of Kirkendall voids were observed at the interface between Cu3Sn and Cu. The void formation resulted in weak bonding between solder and Cu and...

Effect of thermal aging on board level drop reliability for Pb-free BGA packages

The drive for Pb-free solders in the microelectronics industry presents several new reliability challenges. Examples include package compatibility with higher process temperatures, new solder compound failure mechanisms, and the selection of the proper Pb-free alloy to maximize product lifetime. In addition to the challenges posed by the Pb-free material conversion, the migration of market focus from desktop computing to portable applications is changing the critical system failure mode of interest from conventional temperature cycling (T/C) induced solder fatigue opens to drop impact induced solder joint fracture. In this paper a study was conducted to investigate the influence of intermetallic compound (IMC) growth on the solder joint reliability of Pb-free ball grid array (BGA) packages under drop loading conditions. Thermal aging at homologous temperatures between 0.76 and 0.91 with microstructural analysis was conducted to analyze the solid phase IMC growth at the solder to BGA pad interface. Component level,ball shear and pull tests were also conducted to investigate the aging effect on solder joint strength. A key finding from this work is that Kirkendall voids formed at the bulk solder to package bare Cu pad interface under relative low 100/spl deg/C aging. Void formation and coalesce is shown to be the dominant mechanism for solder joint strength and board level drop reliability degradation.

Multichip assembly with flipped integrated circuits

A multichip module process has been developed using flipped-chip interconnection. The process uses plated copper bumps for superior thermal transport characteristics, active silicon as a substrate material for matched expansion properties, on-chip interconnection metallization that allows bumps to be placed over the active circuitry, and conventional wafer fabrication facilities for low-cost production. For successful design and fabrication of multichip assemblies, an organized methodology similar to that which has proved successful in design and assembly of single VLSI circuits was used. This approach involves: computer-aided modeling of the circuit and package for electrical, thermal, and mechanical simulation; test chips for process development and failure mechanism testing; and fabrication of actual demonstration circuits. Verification of function and reliability was then made through temperature cycle testing (-65 degrees C to 150 degrees C), exposure to accelerated moisture environments, and measure of heat dissipation properties. This approach and an example of its application to a multichip module that demonstrated successful performance on the first design pass are described. >

Wire bonds over active circuits

A reliable process-for wire bonding over active integrated circuits, which are subsequently assembled in plastic packages, has been developed. This technology accommodates reducing the silicon die area required for bond pads and for on-chip bussing. Further, it supports area array wire bonding by allowing larger bond pads with relaxed pitch without sacrificing silicon area. This is accomplished by processing an additional metal layer on the wafers protective overcoat for bond pad and bussing metallization. A stress buffer layer of polyimide is applied between the inorganic overcoat and top metal layer. Material characteristics and process requirements that are fully compatible with existing wafer fabrication technology and the wire bond technology required for assembly are defined. Design rules for implementing the process in new chip designs are given. Accelerated reliability tests performed on double-level metal logic devices show no degradation due to these new processes.<<ETX>>

Wafer level packaging of a tape flip-chip chip scale packages

Abstract The advent of chip scale packages (CSPs) within the semiconductor community has led to the development of wafer scale assembly (WSA) or wafer level packaging (WLP) manufacturing in order to raise assembly efficiencies and lower operating costs. Texas Instruments (TI) has developed a unique WLP process for forming flip-chip, ball grid array packages. The die inputs and outputs of the TI CSP are connected through solder bumps to a polyimide film interposer. Solder balls on the other side of the interposer complete the electrical connection to a customer’s printed circuit board. A wafer-sized array of interposers designed to match the pattern of dies on a wafer is aligned and reflowed to a bumped wafer. The TI WLP process is completed by singulating the CSPs from the wafer using standard wafer saw equipment. Attachment of the interposer to the die as well as applying the die and board level solder bumps are carried out in wafer form using a new bumping technology called Tacky Dots™. Tacky Dots uses an array of sticky dots formed in a photosensitive coating laminated to a polyimide film for transferring and attaching solder spheres to semiconductor substrates. A populated film containing one solder sphere per Tacky Dot is positioned over the wafer or interposer and lowered until the spheres contact the pads. A reflow process transfers the spheres from the film to the wafer or interposer and the film is removed once the spheres have frozen. This paper illustrates the process steps and custom equipment developed for forming the TI CSP. The strategic use of finite element modeling for optimizing the design of the package is outlined. The paper concludes by summarizing the current package level reliability results.

Tacky Dots/sup TM/ transfer of solder spheres for flip chip and electronic package applications

The use of preformed solder spheres for bumping flip chip wafers has not gained wide acceptance within the semiconductor industry. Due in part to equipment shortcomings, solder sphere transfer until now was commonly limited to spheres 300 /spl mu/m or larger, much too large for the typical flip chip applications of 150 /spl mu/m or less. To address this need, Texas Instruments and DuPontB have jointly developed a process for transferring 127 /spl mu/m diameter solder spheres to wafers. The process, called Tacky Dots/sup TM/, forms are array of sticky or tacky dots in a photoimageable adhesive coating. Solder spheres sprinkled on the adhesive coating are then captured and retained by the tacky dots until the spheres are aligned and reflowed to the wafer. This paper describes the equipment and processes developed for bumping wafers using Tacky Dots/sup TM/. The compliant polyimide sheet used in Tacky Dots/sup TM/ required a new and unique equipment design that aligns the solder spheres to the wafer and then reflows the solder without moving the wafer. Post reflow analysis of the bumped dies before and after environmental testing is reviewed. Tests conducted with a leadless chip carrier package design are also reviewed to demonstrate the capability of Tacky Dots/sup TM/ at transferring spheres to electronic packages and substrates other than wafers.

Root Cause of Black Pad Failure of Solder Joints with Electroless Nickel/Immersion Gold Plating

Publications on the so called black pad defect, seen in electroless nickel/immersion gold (ENIG) surface finishes, often cite high phosphorous (P) content in the nickel (Ni) plating as a key factor in the defect. Therefore, one proposed solution is to decrease the P content in the electroless Ni plating. In a contrary approach, some researchers propose a high P content to avoid the black pad defect. In the present work, the solder reaction with ENIG plating and the resulting interfacial structures were studied. Focused ion beam (FIB) was used to polish the cross sections to reveal details of the microstructure of the ENIG plated pad with and without soldering. High speed pull testing of solder joints was performed to expose the pad surface. Results of SEM/EDX analysis of the cross sections and fractured pad surfaces support the suggestion in the literature that black pad is the result of galvanic hyper-corrosion of the plated electroless Ni by the gold (Au) plating bath. High P content in the fractured surface on the pad side is not the signature of black pad. New criteria are proposed for diagnosing black pad in ENIG

Tacky Dots/sup TM/ technology for flip chip and BGA solder bumping

As the electronics market moves toward higher performance Integrated Circuits (ICs), each IC requires larger numbers of Inputs and Outputs (I/Os). This has resulted in a strong need in the marketplace for a low cost, high resolution method for placing controlled volumes of solder (or other metal alloys) on bond pads of ICs and area array semiconductor packages, such as Ball Grid Arrays (BGAs), and Chip Scale Packages (CSPs). To satisfy this need, DuPont has developed the concept of Tacky Dots/sup TM/, which utilizes proprietary technology in photoimageable adhesives to form a pattern of tacky areas, which are subsequently populated with conductive particles and then transferred to ICs or packages. DuPonts expertise and effort have been focused on developing a systems approach to the front end population process, while working closely with Texas Instruments who has developed technology to enable the effective transfer of the conductive particles. This paper contains details of the imaging and population technology as well as a discussion of the overall progress of this new wafer bumping process.