Rohan Mukherjee

Efficient architecture of adaptive rood pattern search technique for fast motion estimation

This paper presents efficient VLSI architecture for fast Motion Estimation (ME) using Adaptive Rood Pattern Search (ARPS) technique. The proposed architecture uses a single processing element (PE) and simplified memory addressing to reduce the hardware complexity. The addressing logic, which is presently applied to 352i?288 CIF frames, can be easily extended to frames of higher resolutions. The proposed architecture uses optimum area while satisfying speed requirements for real-time video processing. Implemented in Verilog HDL and mapped to Virtex 6 (XC6VLX75T-3) FPGA, the architecture uses only 165 slice registers and 273 slice LUTs. The architecture can process 240 frames per second while operating at a maximum frequency of 320MHz.

Efficient VLSI design of adaptive rood pattern search algorithm for motion estimation of high definition videos

Block-based motion estimation plays a significant role in video codecs by exploiting and reducing the temporal redundancies that exist between consecutive frames in a video sequence. Adaptive Rood Pattern Search (ARPS) is one of the most popular fast motion estimation algorithms. In this paper, VLSI design for the ARPS algorithm is proposed that involves reasonably limited hardware resource without compromising the real-time speed for transmitting HD videos. To tackle the adaptive nature of the algorithm, the proposed design avoids systolic arrays and introduces novel pattern generation methodology that can tackle the adaptive nature of the algorithm. Further, the design incorporates interleaved memory organization with a well-defined sharing strategy to re-use data and ensures high throughput. Working at a frequency of 112MHz, the present design can process 30 Full HD 1080p (1920×1080) frames using only 47.15K gates. Hence, the proposed VLSI architecture can be incorporated in video codecs that can be suitably used in devices like camcorders, tablets and smart phones.

An efficient VLSI architecture for motion estimation using new three step search algorithm

This paper presents an efficient VLSI architecture for the implementation of Motion Estimation (ME) for real-time video processing using New Three Step Search Algorithm (NTSS). The proposed architecture employs sequential processing of pixels with a view to reduce the hardware complexity and achieve real-time speed requirement simultaneously. A novel memory addressing scheme has been proposed which optimizes the address generation logic. The architecture uses only 4% FPGA slice registers and slice LUTs which translates to an equivalent gate count of 3.5K. The proposed architecture can achieve a frequency of 350 MHz and is able to process 206 CIF frames per second. It can be included in commercial equipments like camcorders, smart-phones, tablet computers etc.

Fast adaptive motion estimation algorithm and its efficient VLSI system for high definition videos

Abstract Motion estimation (ME) plays an important part in the functioning of the video codec by identifying and reducing the temporal redundancies in between successive frames of a video sequence. Block matching algorithm (BMA) has been accepted as one of the finest approaches for motion estimation due to its efficiency and ease of implementation. This paper presents a new and improved iterative and adaptive search strategy for block-based motion estimation along with its efficient hardware implementation. Since it is expected that there will be more demand for streaming video services on mobile devices, designing fine tuning algorithm with dedicated efficient hardware would provide significant benefits. The present motion estimation algorithm is adaptive in nature that takes into consideration the motion content of the current frame while predicting the motion vector. The adaptive nature of the search eases the complexity of motion estimation and the algorithm makes use of the correlation present among the motion vectors of the neighboring blocks to lower the number of search position. Traditionally, such adaptive algorithms are executed by CPU cores running a software stack. Since software involves a significant amount of overheads like fetching into cache, branches, stalls etc., the efficiency of the proposed algorithm can be overshadowed by the hardware platform. To avoid this, compact hardware architecture was developed which stands ahead of other existing architectures as shown in comparison. The VLSI design for the proposed algorithm presented in this work deals with the generation of the adaptive search pattern and use of interleaved memory organization fasten the operational speed. A profitable data re-use scheme and involvement of minimum processing elements required for parallelization reduce the on-chip area. Working at a frequency of 243 MHz, the proposed design can process 66 720p HD (1280 × 720) frames in one second consuming an area of 38.2 K gate equivalent. Hence, the proposed design can be incorporated in video codecs to be used in commercial devices like camcorders, smart phones and other portable, battery-powered video consumer devices. The proposed research method achieves significantly improved results both in terms of algorithmic metrics (PSNR) as well hardware performance (speed, area).

A High-Speed VLSI Architecture for Motion Estimation Using Modified Adaptive Rood Pattern Search Algorithm

The paper presents an efficient VLSI architecture for fast Motion Estimation in video codec using modified Adaptive Rood Pattern Search Algorithm. The proposed architecture uses an interleaved memory arrangement and an early check technique to compute the Sum of Absolute Differences. The proposed design can process High Definition (1080p) video frames in real time while optimizing the hardware area. The architecture has been implemented in verilog HDL and mapped to 45 nm FPGA. It uses only 6.8K gates for the implementation of the datapath and the controller. It achieves a maximum frequency of 120 MHz. However, working at 100 MHz, it is able to process 60 HD (

An efficient FPGA based implementation of forward integer transform and quantization algorithm of H.264

1920\times 1080

High performance VLSI implementation of CAVLC decoder of H.264/AVC for HD transmission

1920×1080) frames per second while consuming 39 mW of power. The proposed architecture achieves premium speed with an optimum power and area requirements and can be suitably incorporated in light-weight video-intensive devices like smart-phones, tablet computers.

High performance VLSI implementation of Context-based Adaptive Variable Length Coding (CAVLC) for H.264 encoder

Motion estimation (ME) accounts for the major part of computational complexity of any video coding standard. The diamond search (DS) algorithm is widely used as a fast search technique to perform motion estimation. In this paper, a novel architecture for the diamond search technique is proposed that efficiently handles memory addressing and reduces hardware complexity. The proposed architecture meets the speed requirements for real-time video processing without compromising the area. The design when implemented in Verilog HDL on Virtex-5 technology and synthesized using Xilinx ISE Design Suite 12.4, gives rise to a critical path delay of 3.25 ns and the equivalent area is calculated to be 3.5K gate equivalent. Working at a frequency of 308 MHz, the proposed design can process 128 CIF frames per second. So, the proposed architecture can be incorporated in a video codec targeted for commercial devices like smart-phones, camcorders and video conferencing system.