Rohit Galatage

A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels

We present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology. To overcome optical lithography limits, Extreme Ultraviolet Lithography (EUV) has been introduced for multiple critical levels for the first time. Dual strained channels have been also implemented to enhance mobility for high performance applications.

Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET

In this paper, for the first time we demonstrate that horizontally stacked gate-all-around (GAA) Nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond. It offers increased Weff per active footprint and better performance compared to FinFET, and with a less complex patterning strategy, leveraging EUV lithography. Good electrostatics are reported at Lg=12nm and aggressive 44/48nm CPP (Contacted Poly Pitch) ground rules. We demonstrate work function metal (WFM) replacement and multiple threshold voltages, compatible with aggressive sheet to sheet spacing for wide stacked sheets. Stiction of sheets in long-channel devices is eliminated. Dielectric isolation is shown on standard bulk substrate for sub-sheet leakage control. Wrap-around contact (WAC) is evaluated for extrinsic resistance reduction.

The influence of surface preparation on low temperature HfO2 ALD on InGaAs (001) and (110) surfaces

Current logic devices rely on 3D architectures, such as the tri-gate field effect transistor (finFET), which utilize the (001) and (110) crystal faces simultaneously thus requiring passivation methods for the (110) face in order to ensure a pristine 3D surface prior to further processing. Scanning tunneling microscopy (STM), x-ray photoelectron spectroscopy (XPS), and correlated electrical measurement on MOSCAPs were utilized to compare the effects of a previously developed in situ pre-atomic layer deposition (ALD) surface clean on the InGaAs (001) and (110) surfaces. Ex situ wet cleans are very effective on the (001) surface but not the (110) surface. Capacitance voltage indicated the (001) surface with no buffered oxide etch had a higher C(max) hypothesized to be a result of poor nucleation of HfO2 on the native oxide. An in situ pre-ALD surface clean employing both atomic H and trimethylaluminum (TMA) pre-pulsing, developed by Chobpattana et al. and Carter et al. for the (001) surface, was demonstrated to be effective on the (110) surface for producing low D(it) high C(ox) MOSCAPs. Including TMA in the pre-ALD surface clean resulted in reduction of the magnitude of the interface state capacitance. The XPS studies show the role of atomic H pre-pulsing is to remove both carbon and oxygen while STM shows the role of TMA pre-pulsing is to eliminate H induced etching. Devices fabricated at 120 °C and 300 °C were compared.

MBE growth and digital etch of GaSb/InAs nanowires on Si for logic applications

The 6.1 A III–V “high-mobility” semiconductor family includes materials with beneficial transport properties of both electrons and holes (InAs, GaSb), which are appealing for fast and low-power complementary metal–oxide–semiconductor applications. Yet their large lattice mismatch with Si (∼12%) results in three dimensional island nucleation and therefore growth defects. The solution for deposition of this high mismatch material is the growth of the entire device from a single nucleus, such as in vertical nanowires. Two types of GaSb nanowires (NWs) are demonstrated on a Si(111) substrate: vertically stacked InAs/GaSb NWs and coaxial core/shell NWs. This paper summarizes surface preparation, growth conditions, and postprocessing steps which can be used to create nanowires with small enough diameters for use as logic devices.The 6.1 A III–V “high-mobility” semiconductor family includes materials with beneficial transport properties of both electrons and holes (InAs, GaSb), which are appealing for fast and low-power complementary metal–oxide–semiconductor applications. Yet their large lattice mismatch with Si (∼12%) results in three dimensional island nucleation and therefore growth defects. The solution for deposition of this high mismatch material is the growth of the entire device from a single nucleus, such as in vertical nanowires. Two types of GaSb nanowires (NWs) are demonstrated on a Si(111) substrate: vertically stacked InAs/GaSb NWs and coaxial core/shell NWs. This paper summarizes surface preparation, growth conditions, and postprocessing steps which can be used to create nanowires with small enough diameters for use as logic devices.

Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT

Low Ge content SiGe-based CMOS FinFET is one of the promising technologies [1-2] offering solutions for both high performance and low power applications. In this paper, we established a competitive SiGe-based CMOS FinFET baseline and examined various elements for high performance offering. The performance elements in gate stack, channel doping, contact resistance, and junction have been explored to provide a cumulative 20% / 25% (n/pFET) performance enhancement. These elements provide a viable path towards performance enhancement for future technology nodes.

Electrical properties related to growth defects in metamorphic GaSb films on Si

This paper reports on correlation of growth-related defects and electrical properties in GaSb films grown on different Si substrates using metamorphic buffers. Large lattice mismatch between GaSb and Si (∼11%) results in the formation of threading dislocations (TDs) and microtwins (MTs) along with antiphase domains due to the lack of inversion symmetry in III-Vs. The defect density profiles were analyzed using transmission electron microscopy and atomic force microscopy. The TD density of just below 108 cm−2 and MT density below 104 cm−1 were found in 2.1 μm thick structures, and were found to be four times higher than in similar GaSb structures on GaAs substrates. Hole density and mobility profiles were obtained using differential Hall method and show that dislocations (TDs or MT partials) generate about 25 acceptors/nm. Minimum midgap interface trap density values are similar in the metal-oxide-semiconductor structures prepared on GaAs and Si, ∼2 × 1012 cm2 eV−1.

Formation of atomically ordered and chemically selective Si—O—Ti monolayer on Si0.5Ge0.5(110) for a MIS structure via H2O2(g) functionalization

Si0.5Ge0.5(110) surfaces were passivated and functionalized using atomic H, hydrogen peroxide (H2O2), and either tetrakis(dimethylamino)titanium (TDMAT) or titanium tetrachloride (TiCl4) and studied in situ with multiple spectroscopic techniques. To passivate the dangling bonds, atomic H and H2O2(g) were utilized and scanning tunneling spectroscopy (STS) demonstrated unpinning of the surface Fermi level. The H2O2(g) could also be used to functionalize the surface for metal atomic layer deposition. After subsequent TDMAT or TiCl4 dosing followed by a post-deposition annealing, scanning tunneling microscopy demonstrated that a thermally stable and well-ordered monolayer of TiOx was deposited on Si0.5Ge0.5(110), and X-ray photoelectron spectroscopy verified that the interfaces only contained Si-O-Ti bonds and a complete absence of GeOx. STS measurements confirmed a TiOx monolayer without mid-gap and conduction band edge states, which should be an ideal ultrathin insulating layer in a metal-insulator-semiconductor structure. Regardless of the Ti precursors, the final Ti density and electronic structure were identical since the Ti bonding is limited by the high coordination of Ti to O.

Selective GeO x -scavenging from interfacial layer on Si 1−x Ge x channel for high mobility Si/Si 1−x Ge x CMOS application

We demonstrate a technique for selective GeO_x-scavenging which creates a GeO_x-free IL on Si_1-xGe_x substrates. This process reduces N_it by >60% to 2e11 and increases high-field mobility at N_inv=1e13 cm^-2 by ~1.3× in Si_0.6Ge_0.4 pFETs with sub-nm EOT.

(Invited) Rapid In-Situ Carbon and Oxygen Cleaning of In0.53Ga0.47As(001) and Si0.5Ge0.5(110) Surfaces via a H2 RF Downstream Plasma

The In0.53Ga0.47As(001) and Si0.5Ge0.5(110) surfaces were cleaned using a downstream RF plasma. On the air-exposed In0.53Ga0.47As(001) surface, a 2 second 100 millitorr H2 plasma dose fully removed carbon and oxygen. On the ex-situ wet cleaned Si0.5Ge0.5(110) surface, nearly all carbon and oxygen are removed via a 2 second exposure of 5% H2 in Ar plasma. To prevent oxygen deposition from the plasma tube while maximizing the atomic H flux, for Si0.5Ge0.5(110), the plasma power, pressure, and gas composition must be controlled. The Si0.5Ge0.5(110) surface is more sensitive than the In0.53Ga0.47As(001) surface to trace oxygen in the plasma stream consistent with the higher heat of formation per Si of SiO2 than the heat of formation per Ga of Ga2O3. The higher heat of formation of SiO2 is expected to both increase oxygen adsorption and prevent the atomic H from forming volatile products with SiO2 on Si0.5Ge0.5(110), in contrast to In0.53Ga0.47As(001).