Robin Chao

A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels

We present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology. To overcome optical lithography limits, Extreme Ultraviolet Lithography (EUV) has been introduced for multiple critical levels for the first time. Dual strained channels have been also implemented to enhance mobility for high performance applications.

Towards electrical testable SOI devices using Directed Self-Assembly for fin formation

The first fully integrated SOI device using 42nm-pitch directed self-assembly (DSA) process for fin formation has been demonstrated in a 300mm pilot line environment. Two major issues were observed and resolved in the fin formation process. The cause of the issues and process optimization are discussed. The DSA device shows comparable yield with slight short channel degradation which is a result of a large fin CD when compared to the devices made by baseline process. LER/LWR analysis through the DSA process implied that the 42nm-pitch DSA process may not have reached the thermodynamic equilibrium. Here, we also show preliminary results from using scatterometry to detect DSA defects before removing one of the blocks in BCP.

Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET

In this paper, for the first time we demonstrate that horizontally stacked gate-all-around (GAA) Nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond. It offers increased Weff per active footprint and better performance compared to FinFET, and with a less complex patterning strategy, leveraging EUV lithography. Good electrostatics are reported at Lg=12nm and aggressive 44/48nm CPP (Contacted Poly Pitch) ground rules. We demonstrate work function metal (WFM) replacement and multiple threshold voltages, compatible with aggressive sheet to sheet spacing for wide stacked sheets. Stiction of sheets in long-channel devices is eliminated. Dielectric isolation is shown on standard bulk substrate for sub-sheet leakage control. Wrap-around contact (WAC) is evaluated for extrinsic resistance reduction.

Multitechnique metrology methods for evaluating pitch walking in 14 nm and beyond FinFETs

Abstract. Integrated circuits from 22-nm node and beyond utilize many innovative techniques to achieve features that are well beyond the resolution limit of 193-nm immersion lithography. The introduction of complex three-dimensional structures in device design presents additional challenges that require more sophisticated metrology with high accuracy and precision. One such example is pitch walking induced by multiple-patterning techniques. Quantification of pitch walking has traditionally been a challenge. We present two ways of detecting pitch walking using optical and x-ray techniques. In scatterometry, this work investigates the feasibility of nonorthogonal azimuth angle spectroscopic reflectometry setups for fin pitch walking measurements, which is useful for in-line monitoring in 14-nm node microelectronics manufacturing. Simulations show a significant improvement in pitch walking sensitivity using 45-deg azimuth scan. Other relevant considerations for pitch walking modeling in scatterometry, such as parameter correlations, are also discussed. Another approach is using high-resolution x-ray diffraction (HRXRD) to measure the diffraction peaks from crystalline fins. The onset of pitch walking is determined by the appearance of a shifted subset of peaks in the diffraction spectrum. Information about the fin profiles, e.g., sidewall angle, critical dimension, height, and pitch walking, can be obtained from the resultant diffraction pattern. Note that in HRXRD measurements, each critical parameter is a unique element in the Reciprocal Space Map (RSM) and no correlations between parameters exist. We will discuss the results from measurements using the two techniques and how the combination of the two techniques can give complete information about the fins needed for in-line monitoring.

Novel in-line metrology methods for Fin pitch walking monitoring in 14nm node and beyond

Integrated circuits from 22nm node and beyond utilize many innovative techniques to achieve features that are well beyond the resolution limit of 193nm immersion lithography. The introduction of complex 3D structures in device design presents additional challenges that require more sophisticated metrology with high accuracy and precision. One such example is pitch walking induced by multiple-patterning techniques. Quantification of pitch walking has traditionally been a challenge. In this paper, we present two ways of detecting pitch walking using optical and X-ray techniques. In scatterometry, this work investigates the feasibility of non-orthogonal azimuth angle spectroscopic reflectometry setups for Fin pitch walking measurements, which is useful for in-line monitoring in 14nm node microelectronics manufacturing. Simulations show a significant improvement in pitch walking sensitivity using 45 degree azimuth scan. Other relevant considerations for pitch walking modeling in scatterometry, such as parameter correlations, are also discussed. Another approach is using high-resolution X-ray diffraction (HRXRD).Which is sensitive to the crystalline films. Pitch walking is seen as additional peaks in the diffraction and the intensities can be used to quantify the pitch walking. In addition, additional information about the Fin profiles, e.g. sidewall angle, CD and height, can be obtained. Note that in HRXRD measurements, all the parameters are deconvolved from the pitch walking. In this paper, we will discuss the results from measurements using the two techniques and how the combination of the two techniques can give complete information about the fins needed for in-line monitoring.

Electrical test prediction using hybrid metrology and machine learning

Electrical test measurement in the back-end of line (BEOL) is crucial for wafer and die sorting as well as comparing intended process splits. Any in-line, nondestructive technique in the process flow to accurately predict these measurements can significantly improve mean-time-to-detect (MTTD) of defects and improve cycle times for yield and process learning. Measuring after BEOL metallization is commonly done for process control and learning, particularly with scatterometry (also called OCD (Optical Critical Dimension)), which can solve for multiple profile parameters such as metal line height or sidewall angle and does so within patterned regions. This gives scatterometry an advantage over inline microscopy-based techniques, which provide top-down information, since such techniques can be insensitive to sidewall variations hidden under the metal fill of the trench. But when faced with correlation to electrical test measurements that are specific to the BEOL processing, both techniques face the additional challenge of sampling. Microscopy-based techniques are sampling-limited by their small probe size, while scatterometry is traditionally limited (for microprocessors) to scribe targets that mimic device ground rules but are not necessarily designed to be electrically testable. A solution to this sampling challenge lies in a fast reference-based machine learning capability that allows for OCD measurement directly of the electrically-testable structures, even when they are not OCD-compatible. By incorporating such direct OCD measurements, correlation to, and therefore prediction of, resistance of BEOL electrical test structures is significantly improved. Improvements in prediction capability for multiple types of in-die electrically-testable device structures is demonstrated. To further improve the quality of the prediction of the electrical resistance measurements, hybrid metrology using the OCD measurements as well as X-ray metrology (XRF) is used. Hybrid metrology is the practice of combining information from multiple sources in order to enable or improve the measurement of one or more critical parameters. Here, the XRF measurements are used to detect subtle changes in barrier layer composition and thickness that can have second-order effects on the electrical resistance of the test structures. By accounting for such effects with the aid of the X-ray-based measurements, further improvement in the OCD correlation to electrical test measurements is achieved. Using both types of solution incorporation of fast reference-based machine learning on nonOCD-compatible test structures, and hybrid metrology combining OCD with XRF technology improvement in BEOL cycle time learning could be accomplished through improved prediction capability.

Advanced in-line metrology strategy for self-aligned quadruple patterning

Self-Aligned Quadruple Patterning (SAQP) is a promising technique extending the 193-nm lithography to manufacture structures that are 20nm half pitch or smaller. This process adopts multiple sidewall spacer image transfers to split a rather relaxed design into a quarter of its original pitch. Due to the number of multiple process steps required for the pitch splitting in SAQP, the process error propagates through each deposition and etch, and accumulates at the final step into structure variations, such as pitch walk and poor critical dimension uniformity (CDU). They can further affect the downstream processes and lower the yield. The impact of this error propagation becomes significant for advanced technology nodes when the process specifications of device design CD requirements are at nanometer scale. Therefore, semiconductor manufacturing demands strict in-line process control to ensure a high process yield and improved performance, which must rely on precise measurements to enable corrective actions and quick decision making for process development. This work aims to provide a comprehensive metrology solution for SAQP. During SAQP process development, the challenges in conventional in-line metrology techniques start to surface. For instance, critical-dimension scanning electron microscopy (CDSEM) is commonly the first choice for CD and pitch variation control. However, it is found that the high aspect ratio at mandrel level processes and the trench variations after etch prevent the tool from extracting the true bottom edges of the structure in order to report the position shift. On the other hand, while the complex shape and variations can be captured with scatterometry, or optical CD (OCD), the asymmetric features, such as pitch walk, show low sensitivity with strong correlations in scatterometry. X-ray diffraction (XRD) is known to provide useful direct measurements of the pitch walk in crystalline arrays, yet the data analysis is influenced by the incoming geometry and must be used carefully. A successful implementation of SAQP process control for yield improvement requires the metrology issues to be addressed. By optimizing the measurement parameters and beam configurations, CDSEM measurements distinguish each of the spaces corresponding to the upstream mandrel processes and report their CDs separately to feed back to the process team for the next development cycle. We also utilize the unique capability in scatterometry to measure the structure details in-line and implement a “predictive” process control, which shows a good correlation between the “predictive” measurement and the cross-sections from our design of experiments (DOE). The ability to measure the pitch walk in scatterometry was also demonstrated. This work also explored the frontier of in-line XRD capability by enabling an automatic RSM fitting on tool to output pitch walk values. With these advances in metrology development, we are able to demonstrate the impacts of in-line monitoring in the SAQP process, to shorten the patterning development learning cycle to improve the yield.

Hybridization of XRF/XPS and scatterometry for Cu CMP process control

This paper demonstrates the synergy between X-rays techniques and scatterometry, and the benefits to combine the data to improve the accuracy and precision for in-line metrology. Particular example is given to show that the hybridization addresses the challenges of aggressive patterning. In 10nm node back-end-of-line (BEOL) integration, we show that the hybridized data between scatterometry and simultaneous X-Ray Fluorescence (XRF) and X-ray Photoelectron Spectroscopy (XPS) provided the closest dimensional correlation to TEM results compared to the individual technique and CDSEM.

Highly-selective superconformai CVD Ti silicide process enabling area-enhanced contacts for next-generation CMOS architectures

We investigate a novel Ti Chemical Vapor Deposition (CVD Ti) technique for source/drain and trench contact silicidation. This work is a first demonstration of a highly selective, superconformal Ti process that exhibits a low p-type CVD Ti/SiGe:B contact resistivity (pc) down to 2.1×10⁻⁹ Ω.cm² (a 40% reduction vs. PVD Ti), matching the lowest published values [1-5]. A competitive n-type CVD Ti/Si:P with a ρ<inf>c</inf> at 2.6×10⁻⁹ Ω.cm² is measured. We demonstrate up to 90% superconformality for this process, with a tunnel silicidation at lengths up to 500nm, showing an exceptional selectivity to oxide. This process is an enabler for the next generation of area-enhanced contact CMOS architectures.

Materials characterization for process integration of multi-channel gate all around (GAA) devices

Multi-channel gate all around (GAA) semiconductor devices march closer to becoming a reality in production as their maturity in development continues. From this development, an understanding of what physical parameters affecting the device has emerged. The importance of material property characterization relative to that of other physical parameters has continued to increase for GAA architecture when compared to its relative importance in earlier architectures. Among these materials properties are the concentration of Ge in SiGe channels and the strain in these channels and related films. But because these properties can be altered by many different process steps, each one adding its own variation to these parameters, their characterization and control at multiple steps in the process flow is crucial. This paper investigates the characterization of strain and Ge concentration, and the relationships between these properties, in the PFET SiGe channel material at the earliest stages of processing for GAA devices. Grown on a bulk Si substrate, multiple pairs of thin SiGe/Si layers that eventually form the basis of the PFET channel are measured and characterized in this study. Multiple measurement techniques are used to measure the material properties. In-line X-Ray Photoelectron Spectroscopy (XPS) and Low Energy X-Ray Fluorescence (LE-XRF) are used to characterize Ge content, while in-line High Resolution X-Ray Diffraction (HRXRD) is used to characterize strain. Because both patterned and un-patterned structures were investigated, scatterometry (also called optical critical dimension, or OCD) is used to provide valuable geometrical metrology.