Shogo Mochizuki

A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels

We present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology. To overcome optical lithography limits, Extreme Ultraviolet Lithography (EUV) has been introduced for multiple critical levels for the first time. Dual strained channels have been also implemented to enhance mobility for high performance applications.

Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET

In this paper, for the first time we demonstrate that horizontally stacked gate-all-around (GAA) Nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond. It offers increased Weff per active footprint and better performance compared to FinFET, and with a less complex patterning strategy, leveraging EUV lithography. Good electrostatics are reported at Lg=12nm and aggressive 44/48nm CPP (Contacted Poly Pitch) ground rules. We demonstrate work function metal (WFM) replacement and multiple threshold voltages, compatible with aggressive sheet to sheet spacing for wide stacked sheets. Stiction of sheets in long-channel devices is eliminated. Dielectric isolation is shown on standard bulk substrate for sub-sheet leakage control. Wrap-around contact (WAC) is evaluated for extrinsic resistance reduction.

Ti and NiPt/Ti liner silicide contacts for advanced technologies

We discuss the transition to Ti based silicides for source-drain (SD) contacts for 3D FinFET devices starting from the 14nm node & beyond. Reductions in n-FET & p-FET contact resistances are reported with the optimization of metallization process & dopant concentrations. The optimization of SiGe epitaxy and addition of a thin interfacial NiPt(10%) are found to significantly improve p-FET contact performance.

FINFET technology featuring high mobility SiGe channel for 10nm and beyond

SiGe for channel material has been explored as a major technology element after the introduction of FINFET into CMOS technology [1-4]. Research on long channel FETs and discrete short channel FETs demonstrated benefits in mobility [1-4] and reliability [2]. Given the disruption that SiGe FIN brings, every aspect associated with SiGe FIN needs to be carefully studied towards technology insertion. In this paper, we report the latest SiGe-based FINFET CMOS technology development. CMOS FINFETs with Si-FIN nFET and SiGe-FIN pFET is demonstrated as a viable technology solution for both server and mobile applications at 10nm node and beyond.

Sub-

We report record low 8.4 × 10^-10 Ω-cm² n-type S/D contact resistivity with laser-induced solid/liquid phase epitaxy of Si:P inside nano-scale contact trenches. Significant reduction of device resistance and resultant great gain of drain current has been demonstrated in scaled n-FinFETs with a contact length of 20 nm.

10^{-9}~\Omega

We achieved mid-10⁻¹⁰ Ω-cm² n-type S/D contact resistivity (npc) and 1.9×10⁻⁹ Ω-cm² p-type S/D contact resistivity (ppc) by employing laser-induced liquid or solid phase epitaxy (LPE/SPE) of Si:P and Ge:Group-III-Metal metastable alloys inside nano-scale contact trenches. The Ge: Group-III-Metal alloy allows for a metal-Ge Fermi level pinning effect to lower Schottky barrier height (SBH) while reducing both bulk and unipolar heterojunction resistances. Correspondingly, large Ron reduction and Id gain have been realized in scaled n- and p-FinFETs with the contact length of less than 20nm.

-cm2 n-Type Contact Resistivity for FinFET Technology

Low Ge content SiGe-based CMOS FinFET is one of the promising technologies [1-2] offering solutions for both high performance and low power applications. In this paper, we established a competitive SiGe-based CMOS FinFET baseline and examined various elements for high performance offering. The performance elements in gate stack, channel doping, contact resistance, and junction have been explored to provide a cumulative 20% / 25% (n/pFET) performance enhancement. These elements provide a viable path towards performance enhancement for future technology nodes.

FinFET performance with Si:P and Ge:Group-III-Metal metastable contact trench alloys

Precession electron diffraction has been used to systematically measure the deformation in Si/SiGe blanket films and patterned finFET test structures grown on silicon-on-insulator type wafers. Deformation maps have been obtained with a spatial resolution of 2.0 nm and a precision of ±0.025%. The measured deformation by precession diffraction for the blanket films has been validated by comparison to energy dispersive x-ray spectrometry, X-Ray diffraction, and finite element simulations. We show that although the blanket films remain biaxially strained, the patterned fin structures are fully relaxed in the crystallographic planes that have been investigated. We demonstrate that precession diffraction is a viable deformation mapping technique that can be used to provide useful studies of state-of-the-art electronic devices.

Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT

We investigate the mechanism of interfacial layer formation on Si<inf>1−x</inf>Ge<inf>x</inf> (0 < x < 0.5) channel and its correlation to hole mobility. It is found that the mobility degradation in low-Ge-content Si<inf>1−x</inf>Ge<inf>x</inf> (x < 0.2) pFETs is attributed to a Ge-rich top surface in the channel directly induced by interfacial layer formation. In addition, the depth profile of a Si-rich top surface in high-Ge-content Si<inf>1−x</inf>Ge<inf>x</inf> channel is presented to understand the surface atomic configuration of Si<inf>1−x</inf>Ge<inf>x</inf> channel as well as mobility enhancement mechanism.

High-precision deformation mapping in finFET transistors with two nanometre spatial resolution by precession electron diffraction

Introduction of a dual beam (DB) millisecond (mSec) or nanosecond (nSec laser annealing in contact module results in a drastic reduction of contact resistivity. Dependence of this benefit on laser annealing parameters is detailed. The annealing power/temperature condition needed for initiating solid or liquid phase epitaxy (SPE, LPE defines a lower process boundary, while impact of laser annealing on transistor parameters, such as Vt and gate stack, defines an upper process boundary and translates to with-in-die (WID Vt variation. Combining DB laser annealing technique with process-friendly layouts enables contact resistance benefit without degrading product level variability.