Roland Kircher

Fabrication of a Si1-xGex Channel Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) Containing High Ge Fraction Layer by Low-Pressure Chemical Vapor Deposition

A method for growing the high-quality strained epitaxial heterostructure of Si/Si1-xGex/Si by low-pressure chemical vapor deposition (CVD) and the fabrication of Si1-xGex-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) with a high Ge fraction layer have been investigated. It is found that lowering of the deposition temperature of the Si1-xGex and Si capping layers is necessary with increasing Ge fraction in order to prevent island growth of the layers. With the use of the optimized fabrication process, Si/Si1-xGex/Si heterostructures with flat surfaces and interfaces were realized, and a high-performance Si0.5Ge0.5-channel MOSFET has been achieved with a large mobility enhancement of about 70% at 300 K and over 150% at 77 K compared with that of a MOSFET without a Si1-xGex channel.

Charge Losses of N-Doped Trench Cells

N-doped trench cells exhibit increased charge losses during the refresh time interval when the cell plate voltage is reduced below 2.5 V. This effect is attributed to tunneling of electrons from the valence band of the n-region into the conduction band thus contributing to the leakage current of the cell. This is verified by numerical simulations which indicate that tunneling will occur preferently at the upper corners of the trench. The tunneling current is calculated based on a modified WKB-approximation using 2D potential and imref distributions.

SITAR-an efficient 3-D simulator for optimization of nonplanar trench structures

A 3-D device simulator which allows the investigation of the electrical behavior of nonplanar trench-type device structures is presented. It has been used to analyze leakage due to punchthrough between neighboring trench capacitors, depending on geometry and doping profiles. Using an analytical model to estimate the leakage current and a completely vectorized solution algorithm for all three semiconductor equations, the program proved to be a very efficient tool for optimizing the cell size of 4- and 16-Mb DRAMs. >

Basic Physical Models

This chapter presents the important transport mechanisms in the semiconducting material, and a detailed discussion of the physical models, which describe the transport phenomena. We will restrict ourselves on the classical description of the transport by the so-called drift-diffusion approximation. This has been successfully applied to the modeling of many device structures for more than one decade. From the present point of view, the classical approach will be the state-of-the-art formalism in three-dimensional device simulation for at least the next decade. Other, more sophisticated approaches for the device modeling, like ballistic transport description or the hydrodynamic model, which give a deeper insight into the device physics, have first to be evaluated in two-dimensional devices, because of their tremendous requirements of computer resources. On the other hand, the goals of two- and three-dimensional modeling are different. The state-of-the-art modeling in two dimensions is concerned mainly with describing the phenomena in the deep sub-micron regime of MOSFETs, whereas the objectives in three dimensions are the influence of the geometry of the device boundaries on the device characteristics. The latter ones can be described with the “classical” transport models. Nevertheless, we will briefly discuss the limits of the classical description.

Discretization of the Semiconductor Equations

The equations together with eqs. (1.1) and (1.3), or (1.6) and (1.7) form a system of coupled elliptical partial differential equations. This system is defined in three-dimensional space under steady state and in four-dimensional space under transient conditions. An analytical solution in accordance with the models described in chapter two is in general not possible. Therefore, we will have to solve the system by numerical methods. It is the target of this chapter to describe how the continuous space connected with the three spatial and the time coordinates is replaced by a finite subspace with discrete coordinates, to be represented on digital computers. Therefore, we will carry out the analysis of our semiconductor device on a discrete mesh in space and time, with difference equations derived from the system of partial differential equations.

Examples: Leakage in DRAM Cell Structures

Dynamic random access memories (DRAMs) are devices where a large amount of information can be bit-wise stored by writing a certain amount of charge into a particular memory cell. A DRAM device contains a large number of these memory cells, which consist of only two separate device structures: the capacitor where the charge corresponding to the information is stored, and the switching transistor which controls the read and write access to the capacitor. This so-called one-transistor cell is characteristic for DRAMs. Because of its simple structure compared with static random access memories (SRAMs) or logic integrated circuits, the memory cell needs only a rather small area, and therefore, DRAMs have the advantage of high integration density. In addition, they provide a large number of identical structures with a relatively simple circuit environment to transfer the stored information to the outer world. These are the reasons why they are commonly used as test vehicles for a new technology generation. On the other hand, due to the restriction of the one-transistor cell the charge in the capacitor has to be refreshed after a certain time interval, the so-called refresh cycle time. This is neccessary because the charged capacitor is floating, i.e. disconnected from the switching or transfer transistor, and some amount of the charge is lost by generation-recombination processes in space charge regions. The refresh cycle time is in the order of 10 to about 100ms. If additional leakage mechanisms are present the resulting charge loss during one refresh cycle may become a serious problem. In the following, the most important leakage mechanisms which can affect the function of the DRAM cell are briefly introduced. Then we will focus on the investigation of one particular leakage mechanism as an illustration for the application of three-dimensional device simulation, and show how simulation can be used to improve and optimize the DRAM cell design. All examples have been investigated by utilizing the three-dimensional device simulator SITAR, which has been developed as a research tool to investigate trench-type device structures in DRAM memory cells, and to optimize efficiently technological parameters for the process engineers engaged in the development of VLSI and ULSI devices. Although SITAR has originally been designed for trench cells, it is steadily developed towards a three-dimensional device simulator for arbitrary device structures. The examples presented in this chapter give only a slight impression on the features and possible applications of this simulator.