Lothar Risch

Planar and vertical double gate concepts

Abstract In this paper, we report a comparative study of different double gate architectures. The main focus is on the fabrication method of two different device concepts developed in our group. The first is a planar version with special SOI wafers or deposited films and the second is a vertical transistor with lithography independent channel length. In addition to a thorough structural analysis we present electrical characteristics of the fabricated devices.

CMOS based arrays of nanogap devices for molecular electronics

In this paper we present a novel nanogap device architecture for molecular electronics which is fully CMOS compatible and non-invasive to the contacted self-assembled monolayer. The device exhibits precise control over the electrode spacing. Single cells as well as arrays with electrode distances of 2.5 nm have been realized and characterized in terms of basic functionality and yield. Simulations have revealed scalability for feature sizes down to the ten nanometer regime.

How small can MOSFETs get

Scaling of CMOS technology made possible the key appliances of our information technology society, like the PC, mobile communication, and the internet. Reduction of feature sizes for semiconductor devices continued according to Moores law for the last 25 years in order to achieve higher integration densities, higher speed, lower power consumption, and lower costs. But now, as we approach the sub 100 nm regime, several roadblocks have been predicted for the next generations down to 35 nm. The latest ITRS roadmap 99 describes in detail the challenges which have to be addressed for the future CMOS technology nodes, regarding lithography, metallization, power dissipation, and circuit design. Also for the MOSFET, performance degradation is a big issue. Because this is not a limitation from basic physical laws, novel architectures for MOSFETs will be needed to improve again the electrical characteristics and thus pave the way to much smaller transistors than expected in the past. 25 nm CMOS seems to be feasible using very thin silicon substrates on insulator. Further improvements down to 10 nm are very likely with two gates for the control of the charge carriers. So, it is very likely that CMOS will not end with todays roadmap at 35 nm or even before, but may continue with non bulk devices and fully depleted channels. Finally, tunnelling from source to drain will set an end to the reduction of channel length, which is estimated to be below 5 nm.

Drain leakage mechanisms in fully depleted SOI devices with undoped channel [MOSFETs]

The leakage mechanisms in fully depleted (FD) SOI transistors with undoped channel are investigated. These devices - contrary to partially depleted devices - show a strong V/sub DS/ dependence of the leakage currents. Energy balance simulations, including band to band tunneling effects and impact ionization, have been carried out. Contrary to drift diffusion calculations, these simulations can account for the experimental data and show that the two effects can be separated. In order to reduce these leakage effects, the design of the drain has to be optimised.

Retention time of novel charge trapping memories using Al/sub 2/O/sub 3/ dielectrics

Replacing oxide-nitride-oxide (ONO) dielectrics in charge trapping memories such as SONOS (silicon/ONO/silicon) and NROM (nitrided read only memory) by high-k materials potentially offers improved scaling properties of the devices. In particular, a high dielectric constant of at least one of the three layers allows one to reduce the total equivalent oxide thickness (EOT) thus achieving the same programming electric field as in ONO stacks at reduced voltage. In this study, we evaluate the retention time of charge trapping memories using Al/sub 2/O/sub 3/ as a trapping dielectric and as a control gate dielectric. We find sufficiently large shifts of the threshold voltage allowing for retention times of more than ten years for the Al/sub 2/O/sub 3/ charge trapping memories. High-temperature annealed, polycrystalline layers are found to be more useful than amorphous layers annealed at 400-600/spl deg/C due to better retention time, smaller EOT and flat band shifts and a smaller amount of fixed interface charges.

Characterization of ultra-thin SOI transistors down to the 20 nm gate length regime with scanning spreading resistance microscopy (SSRM)

New device concepts have been introduced to fulfill the demands and scaling requirements of the International Technology Roadmap for Semiconductors (ITRS). This, in turn, increases the demands on the characterization methods, e.g. for the measurement of 2D-carrier profiles, which have to be improved to match. This article reports a comparative study of the electrical and analytical characterization of nanoscaled ultra-thin (UT) n-channel and p-channel SOI transistors. The devices were fabricated on 45 nm SOI with gate lengths as short as 20 nm. The gates were defined by electron-beam lithography and nanoscale dry etching. We use high resolution scanning spreading resistance microscopy (SSRM) to provide reliable information about the carrier profile and effective gate lengths of the devices. The results of these measurements are compared with electrical results and with high resolution TEM.

Short Channel Vertical Sidewall Transistors

For the first time vertical n-channel MOSFETs with implanted S/D-regions and channel lengths down to 50 nm are presented, fabricated in a standard production line with iline lithography. These 50 nm transistors exhibit an excellent transconductance of 560 μS/μm, but suffer from short channel effects in the subthreshold region. The devices with 100 nm channel length, having a somewhat reduced transconductance of 445 μS/μm, showed a very low off-current of 5 pA/μm. We thereby demonstrate the possibility of integrating a high performance short channel transistor in a conventional CMOS process.