Rolf Krieger

A BDD-based algorithm for computation of exact fault detection probabilities

Signal and fault detection probabilities are widely used in the area of testing. Due to the computational complexity, in most cases only approximated values are computed. A system called PLATO which allows the computation of the exact values for many combinational circuits is described. The implemented algorithms use the recently developed BDD packages as data structure. Besides the description of the algorithms, attention is given to general problems arising with the use of BDDs as data structure. Some new heuristics are presented to deal with these problems.

A hierarchical approach to fault collapsing

One central point of testing is the choice of the fault model and the faults which have to be considered to ensure the correct behaviour of a circuit. The number of faults has a strong influence on the costs which must be paid for in the generation of a test set. For logical fault models this number can be reduced using equivalence relations between faults. Since the complexity of digital circuits is increasing, hierarchical design is becoming more and more important. In this paper, we show that in the case of a hierarchical circuit description often more equivalence relations between faults can be recognized efficiently than in the case of a nonhierarchical description. With respect to the stuck-at fault model, our experiments show that the computation of these equivalence relations can be performed in negligible time and that the number of faults can be reduced considerably.<<ETX>>

A hybrid fault simulator for synchronous sequential circuits

Fault simulation for synchronous sequential circuits is a very time-consuming task. The complexity of the task increases if there is no information available about the initial state of the circuit. In this case, an unknown initial state is assumed which is usually handled by introducing a three-valued logic. It is known that fault simulation based upon this logic only determines a lower bound for the fault coverage achieved by a test sequence. Therefore, we developed a hybrid fault simulator H-FS combining the advantages of a fault simulator using the three-valued logic and of an exact symbolic fault simulator based upon binary decision diagrams. H-FS is able to handle even the largest benchmark circuits and thereby determines fault coverages much more accurately than previous algorithms using the three-valued logic.

PLATO: A Tool for Computation of Exact Signal Probabilities

Signal probabilities and fault detection probabilikies are a factor of importance in the wea of deterministic and random testing of combinational circuits. Because of the computational complexity in most cases merely approximated probabilities are used. In this paper we present a novel algorithm for com.puting the exact values for large circuits using Binary Decision Diagrams. A n implementation of the algorithm shows that it is now possible to obtain exact signal probability values eficiently f o r all ISCAS-benchmark circuits [3] with the exception of the 16-bit multiplier (~6288).

Hybrid Fault Simulation for Synchronous Sequential Circuits

We present a fault simulator for synchronous sequential circuits that combines the efficiency of three-valued logic simulation with the exactness of a symbolic approach. The simulator is hybrid in the sense that three different modes of operation—three-valued, symbolic and mixed—are supported. We demonstrate how an automatic switching between the modes depending on the computational resources and the properties of the circuit under test can be realized, thus trading off time/space for accuracy of the computation. Furthermore, besides the usual Single Observation Time Test Strategy (SOT) for the evaluation of the fault coverage, the simulator supports evaluation according to the more general Multiple Observation Time Test Strategy (MOT). Numerous experiments are given to demonstrate the feasibility and efficiency of our approach. In particular, it is shown that, at the expense of a reasonable time penalty, the exactness of the fault coverage computation can be improved even for the largest benchmark functions.

On optimizing BIST-architecture by using OBDD-based approaches and genetic algorithms

We introduce a two-staged Genetic Algorithm for optimizing weighted random pattern testing in a Built-in-Self-Test (BIST) environment. The first stage includes the OBDD-based optimization of input probabilities with regard to the expected test length. The optimization itself is constrained to discrete weight values which can directly be integrated in a BIST environment. During the second stage, the hardware-design of the actual BIST-structure is optimized. Experimental results are given to demonstrate the quality of our approach.

Random pattern fault simulation in multi-valued circuits

We present a fault simulator for Multi-Valued Logic Networks (MVLN). With this tool we investigate their Random Pattern Testability (RPT). We show for a restricted class of multi-valued circuits that the RPT is better than for two-valued circuits. We point out the relation between redundancies in two- and multi-valued logic networks. Moreover we show that the role of fault simulation for MVLNs is more important than in the binary case. A set of experimental results for large circuits emphasizes the efficiency of our approach.

Structure based methods for parallel pattern fault simulation in combinational circuits

The authors present several methods which accelerate fault simulation for combinational circuits using parallel pattern evaluation. The methods are based on an extensive structure analysis of the considered circuit. On the one hand the developed methods aim at a reduction of fan-out stems for which the fault simulation has to be performed and on the other hand at a reduction of gate evaluations during the fault simulation. Of course, all methods support the use of parallel pattern evaluation.<<ETX>>

FAST-SC: Fast Fault Simulation in Synchronous Sequential circuits

In this paper we present FAST-sc, a fast fault simulator for synchronous sequential circuits. The simulation strategy is based on the recently published parallel sequence fault simulation algorithm (PSF) [7]. FAST-SC contains several features leading to a further performance improvement: On the one hand, the kernel of the PSF algorithm is accelerated. On the other hand, the number of faults that must be injected during fault simulation is reduced. The effectiveness of these methods is illustrated by running FAST-SC on some benchmark circuits [4].

Fast fault simulation in combinational circuits: an efficient data structure, dynamic dominators and refined check-up

Several methods accelerating fault simulation for combinational circuits using parallel pattern evaluation are presented. All methods make use of a very efficient data structure which allows the easy recognition of special situations that can be used to avoid a lot of gate evaluations during explicit fault simulation. An implementation of the concepts shows that the resulting fault simulation algorithm is very fast. The proposals and the improved data structure considerably enhance the performance of the standard algorithm.<<ETX>>