Rolf Seltmann

Challenges in process marginality for advanced technology nodes and tackling its contributors

Process margin is getting critical in the present node shrinkage scenario due to the physical limits reached (Rayleigh’s criterion) using ArF lithography tools. K1 is used to its best for better resolution and to enhance the process margin (28nm metal patterning k1=0.31). In this paper, we would like to give an overview of various contributors in the advanced technology nodes which limit the process margins and how the challenges have been tackled in a modern foundry model. Advanced OPC algorithms are used to make the design content at the mask optimum for patterning. However, as we work at the physical limit, critical features (Hot-spots) are very susceptible to litho process variations. Furthermore, etch can have a significant impact as well. Pattern that still looks healthy at litho can fail due to etch interactions. This makes the traditional 2D contour output from ORC tools not able to predict accurately all defects and hence not able to fully correct it in the early mask tapeout phase. The above makes a huge difference in the fast ramp-up and high yield in a competitive foundry market. We will explain in this paper how the early introduction of 3D resist model based simulation of resist profiles (resist top-loss, bottom bridging, top-rounding, etc.,) helped in our prediction and correction of hot-spots in the early 28nm process development phase. The paper also discusses about the other overall process window reduction contributors due to mask 3D effects, wafer topography (focus shifts/variations) and how this has been addressed with different simulation efforts in a fast and timely manner.

Influence of the process-induced asymmetry on the accuracy of overlay measurements

In the current paper we are addressing three questions relevant for accuracy: 1. Which target design has the best performance and depicts the behavior of the actual device? 2. Which metrology signal characteristics could help to distinguish between the target asymmetry related overlay shift and the real process related shift? 3. How does uncompensated asymmetry of the reference layer target, generated during after-litho processes, affect the propagation of overlay error through different layers? We are presenting the correlation between simulation data based on the optical properties of the measured stack and KLA-Tencor’s Archer overlay measurements on a 28nm product through several critical layers for those accuracy aspects.

28nm node process optimization: a lithography centric view

Many experts claim that the 28nm technology node will be the most cost effective technology node forever. This results from primarily from the cost of manufacturing due to the fact that 28nm is the last true Single Patterning (SP) node. It is also affected by the dramatic increase of design costs and the limited shrink factor of the next following nodes. Thus, it is assumed that this technology still will be alive still for many years. To be cost competitive, high yields are mandatory. Meanwhile, leading edge foundries have optimized the yield of the 28nm node to such a level that that it is nearly exclusively defined by random defectivity. However, it was a long way to go to come to that level. In my talk I will concentrate on the contribution of lithography to this yield learning curve. I will choose a critical metal patterning application. I will show what was needed to optimize the process window to a level beyond the usual OPC model work that was common on previous nodes. Reducing the process (in particular focus) variability is a complementary need. It will be shown which improvements were needed in tooling, process control and design-mask-wafer interaction to remove all systematic yield detractors. Over the last couple of years new scanner platforms were introduced that were targeted for both better productivity and better parametric performance. But this was not a clear run-path. It needed some extra affords of the tool suppliers together with the Fab to bring the tool variability down to the necessary level. Another important topic to reduce variability is the interaction of wafer none-planarity and lithography optimization. Having an accurate knowledge of within die topography is essential for optimum patterning. By completing both the variability reduction work and the process window enhancement work we were able to transfer the original marginal process budget to a robust positive budget and thus ensuring high yield and low costs.

Overlay leaves litho: impact of non-litho processes on overlay and compensation

According to the ITRS roadmap [1], the overlay requirement for the 28nm node is 8nm. If we compare this number with the performance given by tool vendors for their most advanced immersion systems (which is < 3nm), there seems to remain a large margin. Does that mean that today’s leading edge Fab has an easy life? Unfortunately not, as other contributors affecting overlay are emerging. Mask contributions and so-called non-linear wafer distortions are known effects that can impact overlay quite significantly. Furthermore, it is often forgotten that downstream (post-litho) processes can impact the overlay as well. Thus, it can be required to compensate for the effects of subsequent processes already at the lithography operation. Within our paper, we will briefly touch on the wafer distortion topic and discuss the limitations of lithography compensation techniques such as higher order corrections versus solving the root cause of the distortions. The primary focus will be on the impact of the etch processes on the pattern placement error. We will show how individual layers can get affected differently by showing typical wafer signatures. However, in contrast to the above-mentioned wafer distortion topic, lithographic compensation techniques can be highly effective to reduce the placement error significantly towards acceptable levels (see Figure 1). Finally we will discuss the overall overlay budget for a 28nm contact to gate case by taking the impact of the individual process contributors into account.

Role of 3D photo-resist simulation for advanced technology nodes

3D Resist Models are gaining significant interest for advanced technology node development. Correct prediction of resist profiles, resist top-loss and top-rounding are acquiring higher importance in ORC hotspot verification due to impact on etch resistance and post etch results. We would like to highlight the specific calibration procedure to calibrate a rigorous 3D model. Special focus is on the importance of high quality metrology data for both a successful calibration and for allowing a reduction of the number of data points used for calibration [1]. In a productive application the calibration could be performed using a subset of 20 features measured through dose and focus and model validation was done with 500 features through dose and focus. This data reduction minimized the actual calibration effort of the 3D resist model and enabled calibration run times of less than one hour. The successful validation with the complete data set showed that the data reduction did not cause over- fitting of the model. The model is applied and verified at hotspots showing defects such as bottom bridging or top loss that would not be visible in a 2D resist model. The model performance is also evaluated with a conventional CD error metric where CD at Bottom of simulation and measurement are compared. We could achieve excellent results for both metrics using SEM CD, SEM images, AFM measurements and wafer cross sections. Additional modeling criterion is resist model portability. A prerequisite is the separability of resist model and optical model, i.e. the resist model shall characterize the resist only and should not lump characteristics from the optical model. This is a requirement to port the resist model to different optical setups such as another illumination source without the need of re-calibration. Resist model portability is shown by validation and application of the model to a second process with significantly different optical settings. The resist model can predict hot spots and CDs for the second litho process with the same quality as for the process it was calibrated to.

Smart mask ship to control for enhanced on wafer CD performance

In the process of semicondutcor fabrication the translation of the final product requirements into specific targets for each component of the manufacturing process is one of the most demanding tasks. This involves the careful assessment of the error budgets of each component as well as the sensible balancing of the costs implied by the requirements. Photolithographic masks play a pivotal role in the semiconductor fabrication. This attributes a crucial role to mask error budgeting within the overall wafer production process. Masks with borderline performance with respect to the wafer fabrication requirements have a detrimental effect on the wafer process window thus inducing delays and costs. However, prohibitively strict mask specifications will induce large costs and delays in the mask manufacturing process. Thus setting smart control mechanisms for mask quality assessment is highly relevant for an efficient production flow. To this end GLOBALFOUNDRIES and the AMTC have set up a new mask specification check to enable a smart ship to control process for mask manufacturing. Within this process the mask CD distribution is checked as to whether it is commensurable with the advanced dose control capabilities of the stepper in the wafer factory. If this is the case, masks with borderline CD performance will be usable within the manufacturing process as the signatures can be compensated. In this paper we give a detailed explanation of the smart ship control approach with its implications for mask quality.

Laser-written binary OMOG photomasks for high-volume non-critical 193-nm photolithographic layers

Photomasks are key elements of photolithographic processes, implying that their degradation must be reliably monitored and strongly mitigated. Indeed, the photo-induced oxidation of Cr in Cr On Glass (COG) photomasks and the concomitant electrostatic-field migration present in high-volume production using 193-nm photolithographic scanners severely deteriorate the pattern transfer quality, therefore limiting the lifetime of these reticles. To moderate this effect, Opaque MoSi On Glass (OMOG) photomasks, significantly less prone to such degradation, are currently being massively used in leading-edge microfabrication flows. The type of mask fabrication process normally used involving ebeam writing is however not adapted for non-critical photolithographic layers that do not yet benefit from its inherent performances but still suffer from its high cost and its long processing time. It is therefore proposed in this work to combine the simplicity of laser writing and the resistance of MoSi to degradation by using laser-written binary OMOG photomasks for the non-critical layers (e.g. ion-implantation) of a 28-nm production flow. To evaluate one of this new reticle, its pattern transfer fidelity is compared to the one of a laser-written binary COG mask already qualified for production from a photolithographic quality perspective, both masks being treated using the same optical proximity correction (OPC) model. Dispersive and dissipative properties, critical dimension uniformity, pattern linearity and pattern proximity are directly measured on wafer level, subsequently revealing that both photomasks match in terms of OPC parameters. The utilized OPC model is moreover proven robust against the use of both types of masks, consequently making the conversion from COG to OMOG particularly simple. These experimental results therefore qualify the new mask fabrication type and pave the way for a major utilization in high-volume production.

Backside defect printability for contact layer with different reticle blank material

Backside defects are out of focus during wafer exposure by the mask thickness and cannot be directly imaged on wafer. However, backside defects will induce transmission variation during wafer exposure. When the size of backside defect is larger than 200 microns, the shadow of such particles will locally change the illumination conditions of the mask patterns and may result in a long range critical dimension (CD) variation on wafer depending on numerical aperture (NA) and pupil shape. Backside defects will affect both wafer CD and critical dimension uniformity (CDU), especially for two-dimensional (2D) structures. This paper focuses on the printability of backside defects on contact layer using annular and quadrupole illumination mode, as well as using different reticle blank material. It also targets for gaining better understanding of critical sizes of backside defects on contact layer for different reticle blanks. We have designed and manufactured two test reticles with repeating patterns of 28nm and 40nm technology node of contact layers. Programmed chrome defects of varying size are placed on the backside opposite to the repeating front side patterns in order to measure the spatial variation of transmission and wafer CD. The test mask was printed on a bare silicon wafer, and the printed features measured for size by spatial sampling. We have investigated two contact layers with different illumination conditions. One is advance binary with single exposure; another is phase shift mask with double exposure. Wafer CD variation for different backside defect sizes are demonstrated for the two contact layers. The comparison between backside defect size with inter-field and intra-field CD variation is also discussed.

CD control with defect inspection: you can teach an old dog a new trick

Achieving the required critical dimensions (CD) with the best possible uniformity (CDU) on photo-masks has always played a pivotal role in enabling chip technology. Current control strategies are based on scanning electron microscopy (SEM) based measurements implying a sparse spatial resolution on the order of ~ 10-2 m to 10-1 m. A higher spatial resolution could be reached with an adequate measurement sampling, however the increase in the number of measurements makes this approach in the context of a productive environment unfeasible. With the advent of more powerful defect inspection tools a significantly higher spatial resolution of 10-4 m can be achieved by measuring also CD during the regular defect inspection. This method is not limited to the measurement of specific measurement features thus paving the way to a CD assessment of all electrically relevant mask patterns. Enabling such a CD measurement gives way to new realms of CD control. Deterministic short range CD effects which were previously interpreted as noise can be resolved and addressed by CD compensation methods. This in can lead to substantial improvements of the CD uniformity. Thus the defect inspection mediated CD control closes a substantial gap in the mask manufacturing process by allowing the control of short range CD effects which were up till now beyond the reach of regular CD SEM based control strategies. This increase in spatial resolution also counters the decrease in measurement precision due to the usage of an optical system. In this paper we present detailed results on a) the CD data generated during the inspection process, b) the analytical tools needed for relating this data to CD SEM measurement and c) how the CD inspection process enables new dimension of CD compensation within the mask manufacturing process. We find that the inspection based CD measurement generates typically around 500000 measurements with a homogeneous covering of the active mask area. In comparing the CD inspection results with CD SEM measurement on a single measurement point base we find that optical limitations of the inspection tool play a substantial role within the photon based inspection process. Once these shift are characterized and removed a correlation coefficient of 0.9 between these two CD measurement techniques is found. This finding agrees well with a signature based matching approach. Based on these findings we set up a dedicated pooling algorithm which performs on outlier removal for all CD inspections together with a data clustering according to feature specific tool induced shifts. This way tool induced shift effects can be removed and CD signature computation is enabled. A statistical model of the CD signatures which relates the mask design parameters on the relevant length scales to CD effects thus enabling the computation CD compensation maps. The compensation maps address the CD effects on various distinct length scales and we show that long and short range contributions to the CD variation are decreased. We find that the CD uniformity is improved by 25% using this novel CD compensation strategy.

Simulation-based scanner tuning using FlexRay Capability and Scatterometry

Differences in imaging behaviour between lithographic systems of the same wavelength result in variations of optical proximity effects (OPE). A way to compensate these irregularities is through scanner tuning. In scanner tuning, scanner specific adjustments are obtained through the determination of scanner knob sensitivities of relevant structures followed by an optimization to adjust the structure CD values to be close to the desired values. Traditionally, scanner tuning methods have relied heavily on wafer-based CD metrology to characterize both the initial mismatch as well as the sensitivities of CDs to the scanner tuning knobs. These methods have proven very successful in reducing the mismatch, but their deployment in manufacturing has been hampered by the metrology effort. In this paper, we explore the possibility of using ASMLs LithoTuner PatternMatcher FullChip (PMFC) computational lithography tool to reduce the dependence on wafer CD metrology. One tuning application using flexray illumination instead of traditional scanner knobs is presented in this work; in this application individual critical features in wafer printing are improved without affecting other sites. The limited impact of tuning on other structures is verified through full-chip LMC runs. Potential uses of this technology are for process transfers from one fab to another where the OPC signature in the receiving fab is similar but not identical to the signature of the originating fab. The tuning application is investigated with respect to its applicability in a production environment, including further metrology effort reduction by using scatterometry tools.