Tino Hertzsch

Influence of the process-induced asymmetry on the accuracy of overlay measurements

In the current paper we are addressing three questions relevant for accuracy: 1. Which target design has the best performance and depicts the behavior of the actual device? 2. Which metrology signal characteristics could help to distinguish between the target asymmetry related overlay shift and the real process related shift? 3. How does uncompensated asymmetry of the reference layer target, generated during after-litho processes, affect the propagation of overlay error through different layers? We are presenting the correlation between simulation data based on the optical properties of the measured stack and KLA-Tencor’s Archer overlay measurements on a 28nm product through several critical layers for those accuracy aspects.

Improving contact layer patterning using SEM contour based etch model

The patterning of the contact layer is modulated by strong etch effects that are highly dependent on the geometry of the contacts. Such litho-etch biases need to be corrected to ensure a good pattern fidelity. But aggressive designs contain complex shapes that can hardly be compensated with etch bias table and are difficult to characterize with standard CD metrology. In this work we propose to implement a model based etch compensation method able to deal with any contact configuration. With the help of SEM contours, it was possible to get reliable 2D measurements particularly helpful to calibrate the etch model. The selections of calibration structures was optimized in combination with model form to achieve an overall errRMS of 3nm allowing the implementation of the model in production.

Overlay leaves litho: impact of non-litho processes on overlay and compensation

According to the ITRS roadmap [1], the overlay requirement for the 28nm node is 8nm. If we compare this number with the performance given by tool vendors for their most advanced immersion systems (which is < 3nm), there seems to remain a large margin. Does that mean that today’s leading edge Fab has an easy life? Unfortunately not, as other contributors affecting overlay are emerging. Mask contributions and so-called non-linear wafer distortions are known effects that can impact overlay quite significantly. Furthermore, it is often forgotten that downstream (post-litho) processes can impact the overlay as well. Thus, it can be required to compensate for the effects of subsequent processes already at the lithography operation. Within our paper, we will briefly touch on the wafer distortion topic and discuss the limitations of lithography compensation techniques such as higher order corrections versus solving the root cause of the distortions. The primary focus will be on the impact of the etch processes on the pattern placement error. We will show how individual layers can get affected differently by showing typical wafer signatures. However, in contrast to the above-mentioned wafer distortion topic, lithographic compensation techniques can be highly effective to reduce the placement error significantly towards acceptable levels (see Figure 1). Finally we will discuss the overall overlay budget for a 28nm contact to gate case by taking the impact of the individual process contributors into account.

Backside defect printability for contact layer with different reticle blank material

Backside defects are out of focus during wafer exposure by the mask thickness and cannot be directly imaged on wafer. However, backside defects will induce transmission variation during wafer exposure. When the size of backside defect is larger than 200 microns, the shadow of such particles will locally change the illumination conditions of the mask patterns and may result in a long range critical dimension (CD) variation on wafer depending on numerical aperture (NA) and pupil shape. Backside defects will affect both wafer CD and critical dimension uniformity (CDU), especially for two-dimensional (2D) structures. This paper focuses on the printability of backside defects on contact layer using annular and quadrupole illumination mode, as well as using different reticle blank material. It also targets for gaining better understanding of critical sizes of backside defects on contact layer for different reticle blanks. We have designed and manufactured two test reticles with repeating patterns of 28nm and 40nm technology node of contact layers. Programmed chrome defects of varying size are placed on the backside opposite to the repeating front side patterns in order to measure the spatial variation of transmission and wafer CD. The test mask was printed on a bare silicon wafer, and the printed features measured for size by spatial sampling. We have investigated two contact layers with different illumination conditions. One is advance binary with single exposure; another is phase shift mask with double exposure. Wafer CD variation for different backside defect sizes are demonstrated for the two contact layers. The comparison between backside defect size with inter-field and intra-field CD variation is also discussed.