Eric Cotte

193-nm immersion photomask image placement in exposure tools

In case drastic changes need to be made to tool configurations or blank specifications, it is important to know as early as possible under which conditions the tight image placement requirements of future lithography nodes can be achieved. Modeling, such as finite element simulations, can help predict the magnitude of structural and thermal effects before actual manufacturing issues occur, and basic experiments using current tools can readily be conducted to verify the predicted results or perform feasibility tests for future nodes. Using numerical simulations, experimental mask registration, and printing data, the effects on image placement of stressed layer patterning, pellicle attachment, blank dimensional and material tolerances, as well as charging during e-beam writing were investigated for current mask blank specifications. This provides an understanding of the areas that require more work for image placement error budgets to be met and to insure the viability of optical lithography for future nodes.

Pellicle-induced aberrations and apodization in hyper-NA optical lithography

In 193nm optical lithography, immersion technology will enable numerical apertures much greater than 1.0. Furthermore, polarized light is likely to be applied, enhancing the imaging properties of structures with dimensions near the resolution limit. As a result, the consequences of extreme oblique angle illumination as well as polarization effects need to be carefully evaluated for all elements of the lithographic process. This paper explores the aberrations and apodization induced by the pellicle film in hyper NA lithography. In a first step, the angle and polarization-dependent phase errors of a perfectly flat pellicle are investigated and discussed for varying thicknesses. It will be shown that for NAs greater than 1.0 the pellicle induces higher order spherical aberrations which can be in the range of todays scanner lens specifications. Also, the impact of polarizationdependent apodization will be discussed. In a second step, the analysis is extended to the case of a non-flat pellicle due to a given frame bow. Under these conditions, the phase and transmission error is not radially symmetric and, furthermore, is field dependent. It will be discussed under which conditions this effect can lead to a significant pellicle-induced CD signature over the entire image field.

Analysis of the Vistec LMS IPRO3 performance and accuracy enhancement techniques

Following the international technology roadmap for semiconductors the image placement precision for the 65nm technology node has to be 7nm. In order to be measurement capable, the measurement error of a 2D coordinate measurement system has to be close to 2nm. For those products, we are using the latest Vistec registration metrology tool, the LMS IPRO3. In this publication we focus on the tool performance analysis and compare different methodologies. Beside the well-established ones, we are demonstrating the statistical method of the analysis of variance (ANOVA) as a powerful tool to quantify different measurement error contributors. Here we deal with short-term, long-term, orientation-dependent and tool matching errors. For comparison reasons we also present some results based on LMS IPRO2 and LMS IPRO1 measurements. Whereas the short-term repeatability and long-term reproducibility are more or less given by the tool set up and physical facts, the orientation dependant part is a result of a software correction algorithm. We finally analyse that kind of residual tool systematics and test some improvement strategies.

Influence of the process-induced asymmetry on the accuracy of overlay measurements

In the current paper we are addressing three questions relevant for accuracy: 1. Which target design has the best performance and depicts the behavior of the actual device? 2. Which metrology signal characteristics could help to distinguish between the target asymmetry related overlay shift and the real process related shift? 3. How does uncompensated asymmetry of the reference layer target, generated during after-litho processes, affect the propagation of overlay error through different layers? We are presenting the correlation between simulation data based on the optical properties of the measured stack and KLA-Tencor’s Archer overlay measurements on a 28nm product through several critical layers for those accuracy aspects.

Mask performance improvement with mapping

Current high end chips require an extremely precise fabrication of lithographic masks. Some of the most critical parameters are the placement of structures on the masks as well as their dimensional tolerances. Improving these two key parameters has always been one of the central objectives of the Advanced Mask Technology Center (AMTC). To this end, the AMTC has complemented its process development by a set of enhancement schemes which are used to compensate residual process signatures. In this paper, improvements achieved in the area of CD uniformity (CDU) and pattern placement are shown. The correction schemes take first principle considerations as well as empirical findings into account. Based on this, a set of design and process parameters is used to determine the spatial corrections which will optimize mask quality parameters. This enables the AMTC to tailor the writing parameters to the needs of each mask design. Latest results for the 32nm technology show that values as low as 5nm image placement error and 3nm CDU can be reached at the same time.

Modeling the work piece charging during e-beam lithography

Nowadays, high end photomasks are usually patterned with electron beam writers since they provide a superior resolution. However, placement accuracy is severely limited by the so-called charging effect: Each shot with the electron beam deposits charges inside the mask blank which deflect the electrons in the subsequent shots and therefore cause placement errors. In this paper, a model is proposed which allows to establish a prediction of the deflection of the beam and thus provide a method for improving pattern placement for photomasks.

Overlay leaves litho: impact of non-litho processes on overlay and compensation

According to the ITRS roadmap [1], the overlay requirement for the 28nm node is 8nm. If we compare this number with the performance given by tool vendors for their most advanced immersion systems (which is < 3nm), there seems to remain a large margin. Does that mean that today’s leading edge Fab has an easy life? Unfortunately not, as other contributors affecting overlay are emerging. Mask contributions and so-called non-linear wafer distortions are known effects that can impact overlay quite significantly. Furthermore, it is often forgotten that downstream (post-litho) processes can impact the overlay as well. Thus, it can be required to compensate for the effects of subsequent processes already at the lithography operation. Within our paper, we will briefly touch on the wafer distortion topic and discuss the limitations of lithography compensation techniques such as higher order corrections versus solving the root cause of the distortions. The primary focus will be on the impact of the etch processes on the pattern placement error. We will show how individual layers can get affected differently by showing typical wafer signatures. However, in contrast to the above-mentioned wafer distortion topic, lithographic compensation techniques can be highly effective to reduce the placement error significantly towards acceptable levels (see Figure 1). Finally we will discuss the overall overlay budget for a 28nm contact to gate case by taking the impact of the individual process contributors into account.

Mask characterization for double patterning lithography

Double patterning (DPT) lithography is seen industry-wide as an intermediate solution for the 32nm node if high index immersion as well as extreme ultraviolet lithography are not ready for a timely release for production. Apart from the obvious drawbacks of additional exposure, processing steps and the resulting reduced throughput, DPT possesses a number of additional technical challenges. This relates to, e.g., exposure tool capability, the actual applied process in the wafer fab but also to mask performance and metrology. In this paper we will address the mask performance. To characterize the mask performance in an actual DPT process, conventional parameters need to be re-evaluated. Furthermore new parameters might be more suitable to describe mask capability. This refers to, e.g., reticle to reticle overlay but also to CD differences between masks of a DPT reticle set. A DPT target of reticle to reticle induced overlay of 6nm, 3σ at mask level was proposed recently for the 32nm node. The results show that this target can be met. Besides that, local CD variations and local displacement become critical. Finally, the actual mask metrology for determination of these parameters might not be trivial and needs to be set up and characterized properly. In this paper we report on the performance of two-reticle sets based on a design developed to study the impact of mask global and local placement errors on a DPT dual line process. In a first step we focus on reticle to reticle overlay. The overlay between two masks evaluated for different wafer overlay targets is compared with measurements on actual resolution structures. In a second step, mask to mask CD variations are addressed. Off-target CD differences as well as variations of CD signatures on both reticles of a set are investigated. Finally, local CD variations and local displacements are examined. To this aim, local variations of adjacent structures on the reticle are characterized. The contribution of local effects to the overall CD and registration budget is estimated.

Scanner grid recipe creation improvement for tighter overlay specifications

Overlay specifications are tightening with each lithography technology node. As a result, there is a need to improve overlay control methodologies to make them more robust and less time- or effort-consuming, but without any compromise in quality. Two concepts aimed at improving the creation of scanner grid recipes in order to meet evertightening overlay specifications are proposed in this article. Simulations will prove that these concepts can achieve both goals, namely improving overlay control performance and reducing the time and effort required to do so. While more studies are needed to fine-tune the parameters to employ, the trends presented in this paper clearly show the benefits.

Multilayer reticles: advantages and challenges for 28nm chip making

Chip manufacturing with multilayer reticles offers the possibility to reduce reticle cost at the expense of scanner throughput, and is therefore an attractive option for small-volume production and test chips. Since 2010, GLOBALFOUNDRIES Fab 1 uses this option for the 28nm IP shuttles and test chips offered to their customers for development and advance testing of their products. This paper discusses the advantages and challenges of this approach and the practical experience gained during implementation. One issue that must be considered is the influence of the small image field and the asymmetric reticle illumination on the lithographic key parameters, namely layer to layer overlay. Theoretical considerations and experimental data concerning the effects of lens distortion, lens heating, and reticle heating on overlay performance are presented, and concepts to address the specific challenges of multilayer reticles for high-end chip production are discussed.