Roman Kris

Addressing FinFET metrology challenges in 1× node using tilt-beam critical dimension scanning electron microscope

Abstract. At 1× node, a three-dimensional (3-D) FinFET process raises a number of new metrology challenges for process control, including gate height and fin height. At present, there is a metrology gap in inline in-die measurement of these parameters. To fill this metrology gap, in-column beam tilt has been implemented on Applied Materials V4i+ critical dimension scanning electron microscope for height measurement. Low-tilt (5 deg) and high-tilt (14 deg) beam angles have been calibrated to obtain the height and the sidewall angle information. Evaluation of its feasibility and production worthiness is done with applications in both gate height and fin height measurements. Transmission electron microscope correlation with an R2 equal to 0.89 and a precision of 0.81 nm have been achieved on various in-die features in a gate height application. The initial fin height measurement shows less accuracy (R2 being 0.77) and precision (1.49 nm) due to greater challenges brought by the fin profile, yet it is promising for the first attempt. Sensitivity to design of experiment offset die-to-die and in-die variations is demonstrated in both gate height and fin height. The process defect is successfully captured with inline gate height measurement. This is the first successful demonstration of inline in-die gate height measurement for a 14-nm FinFET process control.

Edge roughness characterization of advanced patterning processes using power spectral density analysis (PSD)

Self-Aligned Quadruple Patterning (SAQP) is targeted to support the sub 10nm technology nodes. It is consisted of several process steps starting with lithography and Etch to define the pattern backbone. Followed by additional set of processes based on thin-films deposition and etch that quadruple the number of patterns, shrinking pattern and pitch sizes. Pattern roughness is derived from the physical and chemical characteristics of these process steps. It is changing with each of the SAQP process steps, based on material stack and the etch process characteristics. Relative to a sub 10 nm pattern sizes pattern, edge roughness can significantly impact pattern physical dimensions. Unless controlled it can increase the variability of device electrical performance, and reduce yield. In this paper we present the SAQP process steps and roughness characterization, performed with Power Spectral Density (PSD) methodology. Experimental results demonstrates the ability of PSD analysis to sensitively reflect detailed characterization of process roughness, guiding process development improvements, and enabling roughness monitoring for production.

Advanced edge roughness measurement application for mask metrology

With decreasing Critical Dimensions (CD), the negative influence of line edge roughness (LER) and line-width roughness (LWR) on CD uniformity and mean-to-target CD becomes more pronounced, since there is no corresponding reduction of roughness with dimension reduction. This applies to wafer metrology as well as to mask metrology. In order to better understand the types of roughness as well as the impact of the CD-SEM roughness measurement capabilities on the control of the mask process, the sensitivity and accuracy of the roughness analysis were qualified by comparing the measured mask roughness to the design for a dedicated LER test mask. This comparison is done for different LER amplitude and periodicity values and for reference structures without nominal LER using the built-in CD-SEM algorithms for LER characterization.

CD-SEM application for generic analysis of two-dimensional features on wafers and reticles

SEM Metrology becomes the standard metrology for the mask industry, as the precision and accuracy requirements tighten continuously. At the same time, analysis of general shape features becomes an important task in wafer metrology. In this paper we consider the basic requirements and suggested implementations for performing 2D metrology on reticles and wafers, [i.e. measurements of OPC (Optical Proximity Correction) structures, End of Lines, Dual Damascene and Corner Rounding]. The authors consider the following challenges related to the development of a generic algorithm for general shape 2D analysis: (1) A generic segmentation of the feature. It should be robust to noise, as well as brightness and contrast changes. (2) The complexity of two dimensional general shape features metrology. Standard CD SEM metrology is based on metrics describing simple geometric shapes such as ellipses and lines). (3) Obtaining such metrics that can be used as handles for process control (i.e. what to measure on the 2D feature). In the first part of the paper we describe a novel algorithm for segmentation and geometric analysis of general shape features based on a Smoothing Spline and the methods of differential geometry. Next, we consider the numerical methods implemented for shape analysis of noisy contours. In the second part of the paper the performance of our methods on synthetic contours of circular arc with different noise levels is demonstrated. We conclude with sample results of several suggested metrics measured on real SEM images of reticles and wafers.

Automated mask and wafer defect classification using a novel method for generalized CD variation measurements

Over the years, mask and wafers defects dispositioning has become an increasingly challenging and time consuming task. With design rules getting smaller, OPC getting complex and scanner illumination taking on free-form shapes - the probability of a user to perform accurate and repeatable classification of defects detected by mask inspection tools into pass/fail bins is reducing. The critical challenging of mask defect metrology for small nodes ( < 30 nm) was reviewed in [1]. While Critical Dimension (CD) variation measurement is still the method of choice for determining a mask defect future impact on wafer, the high complexity of OPCs combined with high variability in pattern shapes poses a challenge for any automated CD variation measurement method. In this study, a novel approach for measurement generalization is presented. CD variation assessment performance is evaluated on multiple different complex shape patterns, and is benchmarked against an existing qualified measurement methodology.

Addressing FinFET metrology challenges in 1X node using tilt-beam CD-SEM

At 1X node, 3D FinFETS raise a number of new metrology challenges. Gate height and fin height are two of the most important parameters for process control. At present there is a metrology gap in inline in-die measurement of these parameters. In order to fill this metrology gap, in-column beam tilt has been developed and implemented on Applied Materials V4i+ top-down CD-SEM for height measurement. A low tilt (5°) beam and a high tilt (14°) beam have been calibrated to obtain two sets of images providing measurement of sidewall edge width to calculate height in the host. Evaluations are done with applications in both gate height and fin height. TEM correlation with R2 being 0.89 and precision of 0.81nm have been achieved on various in-die features in gate height application. Fin height measurement shows less accuracy (R2 being 0.77) and precision (1.49 nm) due to challenges brought by fin geometry, yet still promising as first attempt. Sensitivity to DOE offset, die-to-die and in-die variation is demonstrated in both gate height and fin height. Process defect is successfully captured from inline wafers with gate height measurement implemented in production. This is the first successful demonstration of inline in-die gate height measurement for 14nm FinFET process control.

Roughness characterization of gate all around Silicon Nano Wire fabrication

In this paper we present a new methodology to calibrate and correct in line roughness measurements for Silicon Nano Wires (SiNW) fabrication processes. For successful implementation of these processes in industry, the Silicon Nano Wires (SiNW) with widths of 5-25 nm should be characterized in the framework of Secondary Electron Microscope(CD SEM) Metrology. Different smoothing processes yield SiNWs with edge roughness values in the sub nanometer range[1]. Such small differences in roughness values provide an interesting opportunity to evaluate sensitivity of the SEM metrology algorithms and measurement accuracy. A simulation program modeling SEM images including small features was developed, taking into account the main factors that affect the SEM signal formation. Synthetic (simulated) images of SiNW in a range of 5-25 nm and roughness of 0-1 nm were produced. Using synthetic images with added Line Edge Roughness (LER), we characterized the performance and sensitivity of LER algorithms and CD metrics.

Roughness metrology of gate all around silicon nanowire devices

In this paper we present physical characteristics of Silicon Nano Wires (SiNW) fabrication processes, in line SEM metrology measurements, and a new methodology to calibrate and correct in line roughness measurements, improving measurement accuracy. Silicon Nano Wires (SiNW) with widths of 5 - 25 nm were characterized. Hydrogen annealing was shown as a useful method for the fabrication of smooth suspended SiNW that are used to build gate-all-around MOSFETs [1]. Wires that were annealed in H2 exhibit surface roughness below 1 nm along the full length of the 100 nm long suspended wires. Different smoothing processes yield SiNWs with edge roughness values in the sub nanometer range. Such small differences in roughness values, provide an interesting opportunity to evaluate sensitivity of the SEM metrology algorithms and measurement accuracy. A simulation program modeling SEM images including small features was developed, taking into account the main factors that affect the SEM signal formation. Synthetic (simulated) images of SiNW in a range of 5 - 25 nm and roughness of 0 - 1 nm were produced. Using synthetic images with added Line Edge Roughness (LER), we characterized the performance and sensitivity of LER algorithms and metrics. Fabricated SiNW that received various smoothing and thinning treatments were measured with a CD-SEM. Results were compared to calibrate and validate the experimental CD-SEM results.

Inline sidewall angle monitoring of memory capacitor profiles

The integration of embedded ferroelectric random access memory (FRAM) into a standard CMOS flow requires significant control and characterization of the patterned capacitor sidewall angle. The electrical functionality of the FRAM capacitor is highly dependent on the post-etch sidewall characteristics of the TiAlN hardmask and Ir/PZT/Ir capacitor film stack. In this study, we explored various options for determining the sidewall profile of these capacitors including scanning electron microscope (SEM), atomic force microscopy (AFM) and scatterometry. A series of capacitor samples with ranges of sidewall slopes from 60 degrees to 80 degrees was generated to test each measuring techniques robustness. All of the techniques demonstrated relatively accurate sidewall angle measurements of the high-angle capacitor profiles relative to cross-section SEMs. However, the CD SEM had difficulty identifying the top edge of the low-angle capacitor samples due to the large amount of profile roughness, which induced a large measurement error range. Additional optimization is required to improve the CD SEMs precision, before it would be a viable in-line monitor for the FRAM process. The AFM provided good accuracy and precision on the high-angle capacitor profiles, but the tip size limited the measurements to spaces larger than 120 nm. Furthermore, the AFM had a long move-acquire-measure (MAM) time of 5 minutes/site, which limited its throughput as an inline monitor. The scatterometer predicted bottom-stack sidewall angle measurements (2 trapezoid model) that were consistent with the cross-section SEMs, and it produced the lowest across wafer sidewall angle range. It also had the fastest MAM time of 5 seconds/site compared to the other techniques. However, it was difficult to generate an accurate scatterometry model due to the complex optical film stack that incorporated low surface reflectivity and higher surface roughness. While each technique had limitations, scatterometry appeared to be the most capable of inline sidewall angle monitoring.

Advanced 2D structures metrology with CD-SEM for OPC challenges

The rapid shrink of device dimensions requires not only excellent 1D CD precision, but also characterization of corner rounding and line end shape. To meet this on-going trend the industry is in a quest for higher resolution metrology tools, which in-turn drives the use of SEM metrology as more crucial. The industry challenge is to reduce corner rounding and area loss. The metrology challenge, is to be able to measure accurately and precisely these characters, in order to be able to control your process. In our study we will introduce the development of a new algorithm for general shape analysis. The purpose of this algorithm is to allow effective control of the correspondence of the feature’s shape to the design geometry. The disadvantage of the standard CD SEM metric such as contact area was discussed widely in the literature but new metrics were not discussed yet. We consider the following issues and challenges related to the development of a generic algorithm for general shape 2D analysis. First stage of this algorithm is a generic segmentation of the two dimensional features. It should be robust to noise, as well as brightness and contrast changes. Output of this phase will be the contour representing the bottom of the feature. The second stage is the obtaining of new CD metrics for these contours, especially for contours corresponding to contacts with OPC structures. We consider the corner rounding as an example of such new metric. The same techniques can be elaborated for a large range of 2D structures with different levels of complexity. The obtaining of new metrics can be useful as handles for advanced process control (i.e. what to measure on the 2D feature with complex shape such as contact with OPC structures). We consider in this paper the application of the developed metrics for reticle contact with OPC structure monitoring problem that simulates a high level of complexity.