Grzegorz Głuszko

Low temperature mobility in hafnium-oxide gated germanium p-channel metal-oxide-semiconductor field-effect transistors

Effective mobility measurements have been made at 4.2 K on high performance high-k gated germanium p-type metal-oxide-semiconductor field effect transistors with a range of Ge/gate dielectric interface state densities. The mobility is successfully modelled by assuming surface roughness and interface charge scattering at the SiO2 interlayer/Ge interface. The deduced interface charge density is approximately equal to the values obtained from the threshold voltage and subthreshold slope measurements on each device. A hydrogen anneal reduces both the interface state density and the surface root mean square roughness by 20%.

Studies of the quality of GdSiO―Si interface

Abstract In this paper nMOS transistors with GdSiO gate dielectric are studied using electrical methods ( C – V , I – V and charge pumping) in order to assess the quality of the dielectric-semiconductor interface. Mobility is estimated using the split C – V technique and the influence of voltage stress on interface trap generation and charge build-up in the oxide is investigated. Generation of additional interface traps is observed during negative voltage stress only, which may be attributed to hole tunneling from the semiconductor to electron traps. Multi-frequency charge pumping measurements reveal the presence of border traps.

Specialized MEMS microphone for industrial application

This article is an attempt to describe design and verification process of the MEMS+IC (micro-electro-mechanical system assisted by an integrated readout circuit) structure designed in Institute of Electron Technology (ITE) dedicated for specific industrial microphone application. Design tools and methods are presented in this paper along with results of numerical simulations compared with real measurements performed for the key steps of device development.

SOI-Based Microsensors

A silicon-on-insulator (SOI) technology has become a key tool for manufacturing of microsensors. A number of the SOI-based microsensors have been presented in the chapter. The developments are related mostly to non-electrical sensors. Most of them have been developed at Instytut Technologii Elektronowej (ITE) Warsaw, in collaboration with numerous partners. The chapter is divided into two main sections describing the technology and device issues. First, ITE expertise in the area of SOI technologies is described. The SOI CMOS processes based on wafers with a thick and thin device layers are presented. The CMOS technology has become an origin for a PaDEOx technique developed for narrow (order of 100 nm width) line fabrication on the silicon wafers, which allows for development of nanowire-based devices (e.g. multi-gate MOSFETs). The second branch of the SOI technologies, being under development in ITE, includes micromachining techniques. Based on the SOI technologies, a number of devices have been developed with the ITE participation. The following solutions have been presented: monolithic pixel detectors of ionizing radiation, sub-THz radiation detectors based on a concept of radiation-induced plasmon oscillations in the MOSFET channels, smart antennas with a reconfigurable aperture. Next, devices fabricated based on micromachining techniques have been mentioned, e.g. microactuators and probes for scanning thermal microscopy. Finally, development of SOI-based biochemical sensors for small volume sample testing is more widely described. These devices have been manufactured based on the PaDEOx technique and have been applied for analysis of hydrogen an metal ions in water solutions.

MOSFETs in the VeSTIC process - fabrication and characterization

A method for fabrication of VeSFETs, three-dimensional fin-type MOS transistors is presented. The VeSTIC process was developed and experimentally implemented in ITE. The test devics were manufactured, and their electrical characteristics were measured. Methods for extraction of a set of the VeSFET physical parameters are proposed based on the device compact model. The flat-band voltage, mobility and radius of the slit curvature are extracted from the I–V characteristics of a single device.

FDSOI MOSFET threshold voltage characterization based on AC simulation and measurements

A method for extraction of the threshold voltage corresponding to the front and back interface in FDSOI MOSFETs is proposed. The approach is based on the nonlinear behavior of the capacitances between the source and front/back gate. The method has been discussed using the numerical simulation results and has been demonstrated using the C-V characteristics of the experimental FDSOI devices manufactured in ITE.

Electrical characterization of different types of transistors fabricated in VeSTIC process

A development of the VeSTIC technology is reported. The manufacturing of the test structures with different types of transistors is described. The electrical 1-V characteristics of the MOS and junction field effect transistors and of the bipolar junction transistors produced in VeSTIC technology were measured. Basic parameters of the test devices were extracted using the simple device compact models. The technology was assessed taking into consideration the process variability issues.

Bipolar transistor in VESTIC technology: prototype

VESTIC technology is an alternative for traditional CMOS technology. This paper presents first measurement data of prototypes of VES-BJT: bipolar transistors in VESTIC technology. The VES-BJT is a bipolar transistor on the SOI substrate with symmetric lateral structure and both emitter and collector made of polysilicon. The results indicate that VES-BJT can be a device with useful characteristics. Therefore, VESTIC technology has the potential to become a new BiCMOS-type technology with some unique properties.

On-wafer measurements and characterization of poly-si resistors for evaluation of selected CMOS manufacturing processes

In this study, measurements of resistance of polysilicon resistors with different widths have been done over the whole surface of the SOI wafers. The obtained results have been used to determine changes in their width, which is equivalent with shortening of the channel length in the photoli-thography process. By studying the elements distributed across the wafers it was possible to assess the homogeneity of the MOS transistor gate manufacturing process. the abstract two lines below author names and addresses.