Ron Paulsen

Reliability of pFET EEPROM with 70-/spl Aring/ tunnel oxide manufactured in generic logic CMOS Processes

We investigate the reliability of pFET-based EEPROMs with 70-/spl Aring/ tunneling oxides fabricated in standard foundry 0.35-/spl mu/m, 0.25-/spl mu/m, and 0.18-/spl mu/m logic CMOS processes. The floating-gate memory cell uses Fowler-Nordheim tunneling erase and impact-ionization generated hot-electron injection for programming. We show that charge leakage is dominated by the leakage through interlayer dielectrics. We propose a retention model and show the data retention lifetime exceeds 10 years. These results demonstrate the feasibility of producing nonvolatile memory using standard logic processes that have a 70-/spl Aring/ oxide.

Highly Reliable 90-nm Logic Multitime Programmable NVM Cells Using Novel Work-Function-Engineered Tunneling Devices

A highly reliable embedded logic multitime-programmable nonvolatile memory (NVM) has been developed in a standard 90-nm logic process with no process changes and a zero-mask adder. By using a novel work-function-engineered tunneling device and 70-Aring tunneling oxide, an excellent endurance of more than 500 k cycles has been achieved. Reliability of the NVM is evaluated against the traditional tunneling device, and a model is proposed to explain the observed reliability differences. Process manufacturability on retention has also been demonstrated over process variations on the thickness of silicide-blocking layers.

Effect of layout orientation on the performance and reliability of high voltage N-LDMOS in standard submicron logic STI CMOS process

An N-LDMOS (N-channel laterally diffused drain MOSFET), fabricated in a standard CMOS process, is used to provide relatively high-voltage (HV/spl sim/12 V) capability without any extra process steps. However, there is very little information available for LDMOS devices with technologies below 0.35 /spl mu/m using STI isolation. In this work, we investigated the typical layout geometry dependence of device drain current leakage, drain breakdown and on-state current characteristics, with devices fabricated in a standard logic 0.18 /spl mu/m and 0.25 /spl mu/m process. Furthermore, for the first time, a dependence on layout orientation and its effect on hot-carrier injection (HCI) reliability are reported.

Measurement of ultralow gate tunneling currents using floating-gate integrator technique

We report for the first time that a gate tunneling current measurement sensitivity better than 3/spl times/10/sup -22/ A has been achieved by using a floating-gate integrator technique. The technique involves monitoring the charge change in the floating-gate integrated with an on-chip op-amp and an on-chip feedback capacitor. We used this technique to study the stress-induced leakage current (SILC) and its cycling dependence of 70 /spl Aring/ oxides in the direct tunneling region at oxide voltage as low as 1.9 V. The technique has been validated through correlation to direct measurement on MOSFET arrays and theoretical calculations. The measured SILC current is modeled with an Inelastic trap-assisted tunneling model.

Floating-Gate Nonvolatile Memory With Ultrathin 5-nm Tunnel Oxide

Reliability results of floating-gate (FG) memory using 5-nm tunnel oxides in mature (0.25 mum) to advanced (65 nm) logic processes from multiple foundries are reported. Good intrinsic retention is seen across the process nodes studied and for gate oxides as thin as 4.8 nm. With differential memory cells, we also demonstrate promising reliability results with respect to program-cycle-induced tail bits. We conclude that it is possible to develop a small-bit-count FG nonvolatile memory (NVM) array using 5-nm oxide, enabling embedded logic NVM in advanced CMOS processes with no additional masks or processing steps.

Scaling tunneling oxide to 50Å in floating-gate logic NVM at 65nm and beyond

Logic NVM using I/O gate oxide as storage floating gate dielectric developed in baseline logic process does not require extra masks or process steps. Conventional wisdom has suggested that the tunnel oxide of Flash will reach its scaling limits at 6-7 nm due to high reliability requirement for high-density applications. Will FG logic NVM be scalable with tunneling oxide down to 50 A of 2.5 V I/O devices at technology nodes of 65 nm and beyond? In this work, we demonstrate that FG logic NVM with 50 A is readily achievable by performing theoretical statistics analysis and utilizing advanced reliability engineering. Reliability data on FG logic NVM with 50 A tunneling oxide in a standard 65 nm CMOS technology process is also provided.

Charge retention of silicided and unsilicided floating gates in embedded logic nonvolatile memory

Some researchers have previously reported that silicide-blocking layers play a key role in retaining charge in embedded DRAM and Flash memory technologies. In this paper, we investigate the retention characteristics for silicided and unsilicided floating gates embedded logic NVM fabricated in a standard 0.25/spl mu/m logic process. In contrast to previous reports, it is found in this work that silicided and unsilicided NVM have equivalent retention for cycled and un-cycled arrays with temperature bake up to 6120 hrs at 135/spl deg/C. As a result, there is more flexibility in optimizing the memory cell area for logic NVM by removing the silicide-blocking layer.

Reliability of a 90nm Embedded Multi-time Programmable Logic NVM Cells Using Work-function Engineered Tunneling Device

An embedded multi-time programmable (MTP) nonvolatile memory (NVM) has been developed in a standard 90nm logic process. Using a work function engineered tunneling device and 70A tunneling oxide, excellent endurance (>500k cycles) has been achieved. Reliability of the NVM is evaluated against the traditional tunneling device and a model is proposed to explain the observed reliability differences.

Reliability and Qualification of a Floating Gate Memory Manufactured in a Generic Logic Process for RFID Applications

In this paper, we discuss the reliability evaluation and qualification results of a small (~ 256b) pFET based floating gate nonvolatile memory for embedded application in a UHF RFID chip that is being volume produced using a foundry logic CMOS process. The memory is based on bi-directional Fowler-Nordheim tunneling using a ~65-70 Aring oxide that is available from typical foundry processes with 3.3V I/O transistors. Well over one year of retention bake data are reported to show that the memory is reliable for the required applications

A sensitive technique to enable technology transfer and fab matching in deep sub-micron technologies

A sensitive floating-gate integrator technique using single-poly pFET NVM technology has been developed and utilized to enable technology transfer and improved fab matching of logic NVM designs in a standard logic CMOS process. With utilization of our technique, an abnormal parasitic RC relaxation phenomenon observed in a floating gate design was effectively characterized across six foundries and from 0.35 mum to 90 nm logic CMOS technologies. The technique is used as a powerful tool to debug manufacturing issues and to monitor the manufacturability of advanced technologies.