Rong-Shue Hsiao

Enhancement of Hardware-Software Partition for Embedded Multiprocessor FPGA Systems

In this paper, we propose an enhancement partition method that incorporates formal partition, fitting system constraints and hardware orient partition algorithm to solve partitioning issue for embedded multiprocessor FPGA systems. With formal partition, we can rapidly obtain a set of partitioning results that satisfy the system constraints on the number of processors. To fit various system constraints, we find out all partition result sets by fitting system constraints. Finally, hardware orient partition can provide a nearly best partition result for designer to develop multiprocessors system-on-a-chip system. Experiment results show that the proposed method can obtain the fitting best partitioning result than other partitioning method using JPEG encoding system example.

X-clock routing based on pattern matching

In this paper, we propose an X-architecture routing algorithm for a clock network. With the definition of 16-pattern X-routing for a pair of points, our algorithm applies these patterns to simplify the selection of merging segments whereas using the DME approach and constructs an X-clock tree with zero skew. An X-flip is employed to shorten the wire length of each pair of points as possible for minimal clock delay. Moreover, a wire sizing is applied to remove snaking wires for saving routing resource. Experimental results on benchmarks compared with other X-routing algorithms show that our improvements in terms of clock delay, wire length, power consumption, and via cost are 16%, 0.8%, 1.5%, and 17.4%, respectively.

Hardware-oriented Partition for Embedded Multiprocessor FPGA Systems

In this paper, we present hardware-oriented partitioning approach that can solve the partitioning issues for embedded multiprocessor FPGA systems. In addition, it can gain a better partitioning result, faster execution time, less memory and higher slice used rate, under satisfied system constraints. We also demonstrate the feasibility of our approach by a JPEG encoding system using Xilinx ML310 FPGA platform. Experiment results show that the execution time and memory size are improved.

Propagation Delay Minimization on RLC-Based Bus with Repeater Insertion

In this paper, the authors propose a greedy algorithm to minimize the maximal propagation delay for giving the topology of a multi-source multi-sink bus with RLC delay model. The algorithm minimizes the maximal delay by inserting signal repeaters into the critical path and adjusts their sizes, and repeats the above procedure until no any improvement in delay reduction. Experimental results exhibit that the algorithm can reduce the critical delay of a bus effectively for deep submicron technologies. The average savings in critical delay of RLC-based buses for 0.35mum and 0.18mum technologies are less 5.6% and 4% than that of RC-based buses, respectively, whereas the usages in size of RLC-based buses for 0.35mum and 0.18mum technologies are less 3.2 and 13.2 than that of RC-based buses, respectively. The average errors compared with HSPICE in critical delay of RLC-based buses for 0.35mum and 0.18mum technologies are better 3.53% and 1.09% than that of RC-based buses, respectively. The algorithm is simple but very effective

Sophisticated Computation of Hardware-Software Partition for Embedded Multiprocessor FPGA Systems

An embedded multiprocessor FPGA system can provide powerful and more functionalities than single processor system. However, the hardware-software partitioning problem is more complex in system design because the system components become escalation. In this paper, we propose a sophisticated computation method (SCM) to solve hardware-software partitioning issues for embedded multiprocessor FPGA systems. The SCM consists of two levels partition which includes processors-fit level and multi-fit level constraints. In processors-fit level, the partitioning results of unsatisfying processor constraint can be rapidly eliminated. Next, multi-fit level constraints compute various system constraints that based on divide-and-conquer and exhaust methods. Experimental results show that our proposed method can rapidly obtain better partitioning results.

An Integrated Functional Verification Tool for FPGA Systems

Hundreds of thousands circuits can not be verified easily while develop a field programmable gate array (FPGA) system. In this paper, we develop a functional verification tool, namely FVT, to verify the designer defined specification of functionalities with simulator and emulator in a FPGA system. In addition, FVT can point out the exact bugs for functionality where locates at specific cycle. Experiment results show that FVT can save time up to 99%.

A single chip image sensor embedded smooth spatial filter with A/D conversion

The paper presents a current-mode CMOS image sensor embedded smooth spatial filter algorithm. The sensor includes a 66times66 pixel array with an on-chip 6-bit analog-to-digital converter that can identify the output value of pixels in gray level resolution. The last row of pixel cells (1times66) based on the double sampling is used for reducing fixed pattern noise (FPN). Processing circuits are dedicated for the spatial filter algorithm and support reusability to increase the image processing speed and to reduce the design complexity and chip area. The sensor chip has been designed and implemented in TSMC 0.35mum 2P4M CMOS mixed-mode process. Each pixel occupies a area of 15.8mumtimes10.6mum with a fill factor of 37.2%. The power consumption is 35.15mW when the sensor operates at 175 frames/second

Coupling aware RLC-based clock routings for crosstalk minimization

The paper first analyzes the crosstalk interaction for two RLC-based clock routings with considering both coupling capacitance and mutual inductance. Running results based on 0.13mum process show our observations: (a) the difference between clock delays in different frequencies is very small because the damped factor is always larger than 1 for a long-wire clock routing; (b) the crosstalk interaction can be ignored when two parallel segments are far away over than 23mum because the difference between segment delays in a unit length is always less than 3%; (c) the clock delay and skew of two-clock routing with considering crosstalk interaction increase up to 19.1% and 108.8%, respectively. Then, we propose a coupling aware algorithm to generate two-clock routing with considering crosstalk minimization simultaneously. Experimental results show that the clock delay and skew can be improved up to 4.4% and 20%, respectively, than that of no any crosstalk minimization