Trong-Yen Lee

VERTAF: an application framework for the design and verification of embedded real-time software

The growing complexity of embedded real-time software requirements calls for the design of reusable software components, the synthesis and generation of software code, and the automatic guarantee of nonfunctional properties such as performance, time constraints, reliability, and security. Available application frameworks targeted at the automatic design of embedded real-time software are poor in integrating functional and nonfunctional requirements. To bridge this gap, we reveal the design flow and the internal architecture of a newly proposed framework called verifiable embedded real-time application framework (VERTAF), which integrates software component-based reuse, formal synthesis, and formal verification. A formal UML-based embedded real-time object model is proposed for component reuse. Formal synthesis employs quasistatic and quasidynamic scheduling with automatic generation of multilayer portable efficient code. Formal verification integrates a model checker kernel from SGM, by adapting it for embedded software. The proposed architecture for VERTAF is component-based and allows plug-and-play for the scheduler and the verifier. Using VERTAF to develop application examples significantly reduced design effort and illustrated how high-level reuse of software components combined with automatic synthesis and verification can increase design productivity.

New power saving design method for CMOS flash ADC

A new power saving design method for CMOS flash ADC is presented. With an inverter as a comparator along with an NMOS and a PMOS as switches, we use bisection method to let only half of comparators in flash ADC working in every clock cycle. An example of 6-bit flash ADC operates at 200 MHz sampling rate and 3.3 V supply voltage is demonstrated. The power consumption of proposed circuit is only 40.75 mW with HSPICE simulation. Compared with the traditional flash ADC, our bisection method can reduce up to 43.18% in power consumption.

A multi-mode LDO-based Li-ion battery charger in 0.35/spl mu/m CMOS technology

The paper designs a CMOS Li-ion battery charger that uses multi-mode low dropout (LDO) voltage regulator associated with current sense circuit to supply trickle current, large constant current and constant voltage. The whole circuits have been approved by HSPICE with TSMC 0.35/spl mu/m 2P4M CMOS process. The simulation results provide the trickle current of 150mA, the maximum charging current of 312mA and charging voltage of 4.2V at input voltage of 4.5V. The power efficiency of 72.3% is acceptable under the power of 1.28 W.

Enhancement of Hardware-Software Partition for Embedded Multiprocessor FPGA Systems

In this paper, we propose an enhancement partition method that incorporates formal partition, fitting system constraints and hardware orient partition algorithm to solve partitioning issue for embedded multiprocessor FPGA systems. With formal partition, we can rapidly obtain a set of partitioning results that satisfy the system constraints on the number of processors. To fit various system constraints, we find out all partition result sets by fitting system constraints. Finally, hardware orient partition can provide a nearly best partition result for designer to develop multiprocessors system-on-a-chip system. Experiment results show that the proposed method can obtain the fitting best partitioning result than other partitioning method using JPEG encoding system example.

VERTAF: an object-oriented application framework for embedded real-time systems

Embedded real-time applications are often built from scratch on a trial-and-error basis, which leads to sub-optimal designs with latent errors that are not detectable in early stages of use or deployment and often incurs prolonged time-to-market. A new application framework called Verifiable Embedded Real-Time Application Framework (VERTAF) is proposed for embedded real-time application development, with the aim of reducing design errors and increasing design productivity. VERTAF is an integration of three technologies, namely object-oriented technology, software component technology, and formal verification technology. VERTAF consists of five software components: Implanter, Modeler, Scheduler, Verifier, and Generator. Experiences of using VERTAF show a significant increase in design productivity through design reuse, and a significant decrease in design time and effort through design verification. An example shows a relatively low design effort on the part of the designer using VERTAF.

A new low-power turbo decoder using HDA-DHDD stopping iteration

In this paper, we present a new VLSI architecture for a low-power turbo decoder. First, we develop a new soft-in-soft-out decoder architecture and change the sliding window operating flow without attaching LIFO memory. Moreover, we propose a new stopping iteration algorithm that integrates two stop criteria to avoid unnecessary iterations, especially in low SNR channels. Experiments show that our architecture gets 25.3%/spl sim/39.8% memory size saving in our SISO decoder architecture and one window saving of decoding delay in comparison with the traditional decoder.

X-clock routing based on pattern matching

In this paper, we propose an X-architecture routing algorithm for a clock network. With the definition of 16-pattern X-routing for a pair of points, our algorithm applies these patterns to simplify the selection of merging segments whereas using the DME approach and constructs an X-clock tree with zero skew. An X-flip is employed to shorten the wire length of each pair of points as possible for minimal clock delay. Moreover, a wire sizing is applied to remove snaking wires for saving routing resource. Experimental results on benchmarks compared with other X-routing algorithms show that our improvements in terms of clock delay, wire length, power consumption, and via cost are 16%, 0.8%, 1.5%, and 17.4%, respectively.

Embedded software synthesis and prototyping

With the integration of computer technology, consumer products, and communication facilities, the software in an embedded system now accounts for as much as 70% of total system functionalities. In this work, we propose a complete methodology called ESSP (embedded software synthesis and prototyping) for the automatic design of embedded software. Several issues are solved, including software synthesis, software verification, code generation, and system emulation. To avoid design errors, a formal approach is adopted because glitches in embedded software are intolerable and very expensive or even impossible to fix. Complex-choice Petri nets are used to model embedded software, which are then synthesized using an extended quasi static scheduling algorithm. The final generated C code is prototyped on an emulation platform, which consists of an 89C5I microcontroller for executing the software, an FPGA chip for programming the hardware for different applications, and some input/output devices. Two application examples are used to illustrate the feasibility of the ESSP methodology.

Formal synthesis and code generation of real-time embedded software using time-extended quasi-static scheduling

The rapid escalation in complexity of real-time embedded systems design has made embedded software an integral system part such that formal software synthesis has become an indispensable design automation technique. The current work takes one more step forward in this research direction by proposing a formal synthesis method for complex real-time embedded software. Compared to previous work, our method not only synthesizes embedded software with complex interrelated branching choices for execution within a user-given memory bound, but also tries to guarantee the satisfaction of all user-given local and global time constraints. Our proposed method called time-extended quasi-static scheduling (TEQSS) synthesizes real-time embedded software code from a set of time complex-choice Petri nets. The two most important issues in real-time embedded software, namely memory and time constraints are both elegantly and efficiently handled by TEQSS. We show the feasibility of our method through a master-slave role switch application which is a part of the Bluetooth wireless communication protocol.

A new CCII-based pipelined analog to digital converter

This paper proposes a new pipelined analog to digital converter (ADC) based on second-generation current conveyors (CCII). Two main building blocks of the pipelined ADC, sample-and-hold (S/H) circuit and multiplying digital-to-analog converter (MDAC) are constructed of CCII instead of operational amplifiers (OA). Simulation results show that the proposed CCII-based pipelined ADC can work at 10 MHz with an 8-bit resolution. The DNL is within -0.4 LSB and 0.5 LSB and INL is within -0.4 LSB and 0.7 LSB, respectively. The ADC is realized in TSMC 0.35 /spl mu/m CMOS technology and consumed 29 mW under a 3.3 V power supply. The core size is 0.85/spl times/0.85 mm/sup 2/.