Daniel Arumí

Experimental Characterization of CMOS Interconnect Open Defects

Open defects have been intentionally designed in a set of interconnect metal lines. In order to improve the controllability and the observability of the experimental design, a simple bus structure with a scan register followed by a hold register is used to manage the set of interconnect lines. The strength of the open defects has been varied within a realistic range of resistances ranging from a full (complete) open to a weak (low resistance) open by means of broken metal lines and transmission gates, respectively. Experiments performed with an automatic test equipment show the influence of coupling capacitances with adjacent lines on the electrical behavior of the defective line. Furthermore, experimental evidence of the history effect on the delay caused by resistive opens is investigated. Validation of the measured results by means of theoretical as well as simulation analysis is presented. Finally, some recommendations to generate stuck-at, IDDQ and delay test are discussed in order to improve the detectability of such defects.

Diagnosis of Full Open Defects in Interconnecting Lines

A proposal for enhancing the diagnosis of full open defects in interconnecting lines of CMOS circuits is presented. The defective line is first classified as fully opened by means of a logic-based diagnosis tool (Faloc). The proposal is based on the division of the defective line into a number of segments. The selected group of segments is derived from the topology of the line and its surrounding circuitry. The logical information related to the neighbouring metal lines for each considered test pattern is taken into account. With the proposed diagnosis methodology, a set of likely locations for the open defect on the line is obtained. A ranking between the set of possible locations is presented based on the analysis of the quiescent current consumption of the circuit under test. Examples are presented in which the use of the diagnosis methodology is shown to discriminate between different locations of the full open defect.

Full Open Defects in Nanometric CMOS

Full open defects on the interconnect lines cause the broken wires to become floating. The voltage of a floating line depends on its topological characteristics, namely: parasitic capacitances to neighbouring structures, transistor capacitances of the downstream gate(s) and the trapped charge. However, in nanometric CMOS technologies, the oxide thickness is reduced below a few tens of Aring causing the gate tunnelling leakage to strongly impact the behaviour of defective circuits with full open defects. Floating lines can not be considered electrically isolated anymore and are subjected to transient evolutions until arriving at a quiescent state, determined by the technology and the downstream gate(s). The occurrence of full opens as well as the impact of the gate tunnelling leakage is expected to increase for future technologies. The analysis of full opens affecting basic CMOS gates is presented and their defective behaviour characterized. The prediction of the defective logic response of such basic gates is presented for nanometric technologies based on predictive technology models. The final steady state is found to be independent on the initial state of the floating node. Experimental evidence of this behaviour is presented for an industrial chip of 0.18 mum technology.

Diagnosis of full open defects in interconnect lines with fan-out

The development of accurate diagnosis methodologies is important to solve process problems and achieve fast yield improvement. As open defects are common in CMOS technologies, accurate diagnosis of open defects becomes a key factor. Widely used interconnect full open diagnosis procedures are based on the assumption that neighbouring lines determine the voltage of the defective line. However, this assumption decreases the diagnosis efficiency for opens in interconnect lines with fan-out, when the influence of transistor capacitances becomes important. This work presents a diagnosis methodology for interconnect full open defects where the impact of transistor parasitic capacitances is included. The methodology is able to properly diagnose interconnect opens with fan-out even in the presence of Byzantine behaviour. Diagnosis results for real defective devices from different technology nodes are presented.

Delay caused by resistive opens in interconnecting lines

An accurate electrical fault characterization is required for the correct diagnosis and localization of CMOS interconnect defects. It has been traditionally accepted that a resistive open defect located at the beginning of an interconnecting line causes the maximum possible delay. The first-order approximation is sufficient to model the behaviour of high resistive opens. However, in this paper it is shown that low resistive opens do not follow this behaviour. In these cases, a second-order model is required for a more precise prediction of their defective behaviour, since the maximum delay is obtained for an intermediate location, which depends on the relationship between the open resistance, the on-resistance of the transistor network driving the defective net, the parasitic capacitances and the threshold voltage of the transistors driven by the defective net. For that purpose, an experimental circuit has been designed and fabricated where open defects have been intentionally added in a set of interconnect CMOS lines. Both simulation and experimental results on defective interconnect lines show maximum delays for opens located at intermediate positions provided that the resistance of the open is on the order of the on-resistance of the driving transistor network.

Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages

Improvement of diagnosis methodologies is a key factor for fast failure analysis and yield improvement. As bridging defects are a common defect type in CMOS circuits, diagnosing this class of defect becomes relevant for present and future technologies. Bridging defects cause two additional current components, the bridge and the downstream current. This work presents the effect of the downstream current on current signatures and its impact on the diagnosis of such defects. The authors demonstrate that the impact of downstream current is minimized at low power supply (Vdd) values. Therefore, current measurements at low power supply voltages are proposed to enhance bridge diagnosis. Experimental evidence of this behaviour is presented for real devices. Furthermore, current signatures measured at VVLV are used for the diagnosis of fifteen failing 0.18mum technology devices, which are demonstrated to contain a bridging defect.

Time-dependent Behaviour of Full Open Defects in Interconnect Lines

Full open defects on interconnect lines cause broken wires to become floating. The voltage of a floating line depends on its topological characteristics, namely parasitic capacitances to neighbouring structures, transistor capacitances of the downstream gate(s) and trapped charge. However, in nanometer CMOS technologies gate oxide thickness is reduced below a few tens of A, resulting in the gate tunnelling leakage strongly influencing the behaviour of defective circuits with full open defects. Floating lines cannot be considered electrically isolated anymore and are subjected to transient evolutions until reaching a quiescent state, determined by the technology and the downstream gate(s). The occurrence of full opens as well as the impact of gate tunnelling leakage are expected to increase for future technologies. The transient response of full open defects on interconnect lines is analysed for nanometer technologies based on predictive technology models. A method to estimate the delay of defective circuits is proposed. Experimental evidence of this behaviour is presented for a test chip design of 0.18 mum technology.

Post-bond test of Through-Silicon Vias with open defects

Through Silicon Vias (TSVs) are critical elements in three dimensional integrated circuits (3-D ICs) and are susceptible to undergo defects at different stages: during their own fabrication, the bonding stage or during their life time. Typical defects are microvoids, underfilling, misalignement, pinholes in the oxide or misalignments during bonding in such a way that resistive opens become a frequent failure mechanism affecting TSVs. Although there is considerable research effort dedicated to improve TSVs testing, no much attention has been paid to weak defects, especially to weak open defects (resistive opens) causing small delays. In this work, a testing strategy is proposed to detect small delay defects by means of a post-bond oscillation test. Variations in the Duty Cycle of transmitted signals after unbalanced logic gates are shown to detect weak open defects in TSVs. HSPICE simulations including process parameter variations show the effectiveness of the method in the detection of weak open defects above 1 kΩ.

BIST architecture to detect defects in tsvs during pre-bond testing

Through Silicon Vias (TSVs) are critical elements in three dimensional integrated circuits (3-D ICs). The detection of defective TSVs in the earliest process step is of major concern. Hence, testing TSVs is usually done at different stages of the fabrication process. In this context, this work proposes a simple pre-bond GIST architecture to improve the detection of hard and weak defects.

Gate Leakage Impact on Full Open Defects in Interconnect Lines

An Interconnect full open defect breaks the connection between the driver and the gate terminals of downstream transistors, generating a floating line. The behavior of floating lines is known to depend on several factors, namely parasitic capacitances to neighboring structures, transistor capacitances of downstream gate(s) and trapped charges. For nanometer CMOS technologies, the reduction of oxide thickness leads to a significant increase in gate tunneling leakage. This new phenomenon influences the behavior of circuits with interconnect full open defects. Floating lines can no longer be considered electrically isolated and are subjected to transient evolutions, reaching a steady state determined by the technology, downstream interconnect and gate(s) topology. The occurrence of such defects and the impact of gate tunneling leakage are expected to increase in the future. In this work, interconnect full open defects affecting nanometer CMOS technologies are analyzed and the defective logic response of downstream gates after reaching the steady state is predicted. Experimental evidence of this behavior is presented for circuits belonging to a 180 nm and a 65 nm CMOS technologies. Technology trends show that the impact of gate leakage currents is expected to increase in future technologies.