Rourab Paul

Common Readout Unit (CRU) - A new readout architecture for the ALICE experiment

The ALICE experiment at the CERN Large Hadron Collider (LHC) is presently going for a major upgrade in order to fully exploit the scientific potential of the upcoming high luminosity run, scheduled to start in the year 2021. The high interaction rate and the large event size will result in an experimental data flow of about 1 TB/s from the detectors, which need to be processed before sending to the online computing system and data storage. This processing is done in a dedicated Common Readout Unit (CRU), proposed for data aggregation, trigger and timing distribution and control moderation. It act as common interface between sub-detector electronic systems, computing system and trigger processors. The interface links include GBT, TTC-PON and PCIe. GBT (Gigabit transceiver) is used for detector data payload transmission and fixed latency path for trigger distribution between CRU and detector readout electronics. TTC-PON (Timing, Trigger and Control via Passive Optical Network) is employed for time multiplex trigger distribution between CRU and Central Trigger Processor (CTP). PCIe (Peripheral Component Interconnect Express) is the high-speed serial computer expansion bus standard for bulk data transport between CRU boards and processors. In this article, we give an overview of CRU architecture in ALICE, discuss the different interfaces, along with the firmware design and implementation of CRU on the LHCb PCIe40 board.

Novel architecture of modular exponent on reconfigurable system

This paper proposes a single chip solution of the modulus exponent operation for FPGA based embedded system applications. Throughput and resource usage are the two most important issues in the design of embedded systems and the designers must need to choose appropriate hardware architecture to meet these requirements. There are two ways of hardware design namely parallel architecture and sequential architecture. Though sequential architecture has lesser throughput it is suitable for limited resource hardware domain like FPGA based systems. Parallel design may consume huge resources but it has better throughput compare to its sequential counterpart. In this paper, we have proposed the design and implementation of modulus exponent operation in three different ways namely single clock architecture, sequential architecture and a processor core based architecture. The proposed design is implemented and verified on Spartan 3E (XC3S500E-FG320) and Virtex-5, (XC5VLX110T-FF1136) FPGA system. We have used VHDL and SystemC for the various implementations in our work. The results show that our design is better in terms of execution speed and hardware utilization in comparison with the existing research work.

A novel AES-256 implementation on FPGA using co-processor based architecture

Efficient hardware architecture for cryptographic algorithms are of utmost need for implementing secured data communication in embedded applications. The hardware implementation of the algorithms though provides less flexibility, but are faster and requires less resource as compared to the software implementation, and hence ideally suited for target specific embedded systems. Though, there exist quite a few research works that propose hardware design for implementing cryptographic algorithm on various hardware platforms like application specific integrated circuit (ASIC), field programmable gate array (FPGA) and micro-controllers, still there lies the need of better hardware design in terms of larger key values, higher throughput and less resource utilization.

A Novel Method for Soft Error Mitigation in FPGA Using Modified Matrix Code

Field programmable gate arrays (FPGAs) are readily affected by transient faults in the presence of radiation and other environmental hazards compared to application specific integrated circuits. Hence, error mitigation and recovery techniques are necessary to protect the FPGA hardware from soft errors arising from transient faults. In this letter, modified matrix code (MMC) is used for multibit error correction in FPGA-based systems, and dynamic partial reconfiguration is considered to reduce the reconfiguration time. We propose a first of its kind methodology for novel transient fault correction using MMC for FPGAs. To validate the design, the proposed method has been tested on a Kintex FPGA and its performance has been estimated in terms of hardware complexity, power consumption, overhead, and error correction efficiency.

An Efficient Approach to Manage DMA Descriptors and Evaluate PCIe-Based DMA Performance for ALICE Common Readout Unit (CRU)

This paper presents the status of performance evaluation of Peripheral Component Interconnect (PCIe)-based Direct Memory Access (DMA) engine for A Large Ion Collider Experiment-Common Readout Unit (ALICE-CRU) upgrade program using advanced Intel Arria 10 FPGA. The CRU will mainly read out most of the upgraded sub-detectors data and transport the same through the PCIe-DMA engine to server. DMA engine moves data using descriptor. DMA controller pushes those descriptors toward DMA engine. The main goal of this paper is to explain the way DMA engine is to be controlled by DMA controller such that max DMA performance can be achieved. The DMA performance has been evaluated on various server grade machines using Intel Arria 10 FPGA kit (https://www.altera.com/products/boards_and_kits/dev-kits/altera/kit-a10-gx-fpga.html, [1]). The result is around 95% of theoretical DMA engine bandwidth.

Implementation and Evaluation of Glue Logic for Various Configuration Schemes Based on I2C and HDLC Protocol for ALICE Common Readout Unit (CRU)

This paper presents the preliminary results of various configuration schemes for onboard and off-board components using built-in Peripheral Component Interconnect (PCIe) interface of Intel Arria 10 FPGA. This is part of A Large Ion Collider Experiment-Common Readout Unit (ALICE-CRU) upgrade program that will configure CRU itself as well as associated on-detector ASICs of most of the sub-detectors prior data acquisition. In this paper, the different configuration schemes based on Inter-Integrated Circuit (I2C) and High-level Data Link Control (HDLC) protocol will be explained. The main motivation of this paper is to discuss the glue logics that have been developed during evaluation of those protocols. The result obtained during evaluation will also be presented.

Error Resilient Secure Multi-gigabit Optical Link Design for High Energy Physics Experiment

This paper presents a novel design for single channel error resilient secured multi-gigabit optical link for High-Energy Physics (HEP) experiment. The work discusses the logic core implemented on the latest Altera high performance Arria10 FPGA board, having 20nm chip technology. A novel data communication scheme is proposed for this HEP experiment that preserves the DC-balance of the line and allows forward error correction (FEC) with encryption. It is implemented through concatenated blocks of Scrambler, Golay triple error correction coder, AES (Advanced Encryption Standard) cipher and Helical Interleaver. The link operates at a frequency of 8.192 Gbps. Novelty of our design is justified through the performance measurement of the minipod-optical transmitters/receivers.