Suman Sau

Design and implementation of real time secured RS232 link for multiple FPGA communication

Field Programmable Gate Array (FPGA) devices are coming very strongly in the digital hardware systems due to the availability of ready to use resources, parallel logic operations and reconfigurable designs. The usage of FPGA systems in real time domain is also a very fruitful proposition as the FPGA devices are coming with processing cores for Real Time data processing. In a complex system scenario involving a large amount of processing tasks, there is a requirement of building the system using multiple FPGA devices. To make this possible we have to establish a real time data communication between the FPGA devices and to make it even better we have to apply data encryption techniques for making this communication secured. In this paper we demonstrate the design and implementation of a 32-bit RSA algorithms by developing suitable Hardware and Software design on Xilinx Spartan- 3E (XC3S500E-FG320) device, the implementation has been tested successfully for real time serial data communication between multiple FPGA devices using the RS232 serial interface. This development work is also useful for the embedded applications, which requires on board execution of security algorithms. The system is optimized in terms of execution speed and also has been verified using real time debugging tools.

Internal monitoring of GBTx emulator using IPbus for CBM experiment

The Compressed Baryonic Matter (CBM) experiment is a part of the Facility for Antiproton and Ion Research (FAIR) in Darmstadt at GSI. In CBM experiment a precisely time synchronized fault tolerant self-triggered electronics is required for Data Acquisition (DAQ) system in CBM experiments which can support high data rate (up to several TB/s). As a part of the implementation of the DAQ system of Muon Chamber (MUCH) which is one of the important detectors in CBM experiment, a FPGA based Gigabit Transceiver (GBTx) emulator is implemented. Readout chain for MUCH consists of XYTER chips (Front end electronics) which will be directly connected to detector, GBTx emulator, Data Processing Board (DPB) and First level event selector board (FLIB) with backend software interface. GBTx emulator will be connected with the XYTER emulator through LVDS (Low Voltage Differential Signalling) line in the front end and in the back end it is connected with DPB through 4.8 Gbps optical link. IPBus over Ethernet is used for internal monitoring of the registers within the GBTx. In IPbus implementation User Datagram Protocol (UDP) stack is used in transport layer of OSI model so that GBTx can be controlled remotely. A Python script is used at computer side to drive IPbus controller.

A novel AES-256 implementation on FPGA using co-processor based architecture

Efficient hardware architecture for cryptographic algorithms are of utmost need for implementing secured data communication in embedded applications. The hardware implementation of the algorithms though provides less flexibility, but are faster and requires less resource as compared to the software implementation, and hence ideally suited for target specific embedded systems. Though, there exist quite a few research works that propose hardware design for implementing cryptographic algorithm on various hardware platforms like application specific integrated circuit (ASIC), field programmable gate array (FPGA) and micro-controllers, still there lies the need of better hardware design in terms of larger key values, higher throughput and less resource utilization.

A Novel Method for Soft Error Mitigation in FPGA Using Modified Matrix Code

Field programmable gate arrays (FPGAs) are readily affected by transient faults in the presence of radiation and other environmental hazards compared to application specific integrated circuits. Hence, error mitigation and recovery techniques are necessary to protect the FPGA hardware from soft errors arising from transient faults. In this letter, modified matrix code (MMC) is used for multibit error correction in FPGA-based systems, and dynamic partial reconfiguration is considered to reduce the reconfiguration time. We propose a first of its kind methodology for novel transient fault correction using MMC for FPGAs. To validate the design, the proposed method has been tested on a Kintex FPGA and its performance has been estimated in terms of hardware complexity, power consumption, overhead, and error correction efficiency.

An FPGA-Based High-Speed Error Resilient Data Aggregation and Control for High Energy Physics Experiment

Due to the dramatic increase of data volume in modern high energy physics (HEP) experiments, a robust high-speed data acquisition (DAQ) system is very much needed to gather the data generated during different nuclear interactions. As the DAQ works under harsh radiation environment, there is a fair chance of data corruption due to various energetic particles like alpha, beta, or neutron. Hence, a major challenge in the development of DAQ in the HEP experiment is to establish an error resilient communication system between front-end sensors or detectors and back-end data processing computing nodes. Here, we have implemented the DAQ using field-programmable gate array (FPGA) due to some of its inherent advantages over the application-specific integrated circuit. A novel orthogonal concatenated code and cyclic redundancy check (CRC) have been used to mitigate the effects of data corruption in the user data. Scrubbing with a 32-b CRC has been used against error in the configuration memory of FPGA. Data from front-end sensors will reach to the back-end processing nodes through multiple stages that may add an uncertain amount of delay to the different data packets. We have also proposed a novel memory management algorithm that helps to process the data at the back-end computing nodes removing the added path delays. To the best of our knowledge, the proposed FPGA-based DAQ utilizing optical link with channel coding and efficient memory management modules can be considered as first of its kind. Performance estimation of the implemented DAQ system is done based on resource utilization, bit error rate, efficiency, and robustness to radiation.

Integration of GBTx emulator with MUCH-XYTER and data processing board for CBM experiment

The Compressed Baryonic Matter (CBM) experiment is a part of the Facility for Antiproton and Ion Research (FAIR) at Darmstadt, Germany. The challenge in CBM experiment is to measure the particles generated in nuclear collisions with unprecedented precision and statistics. To capture the data from each collision a highly time synchronized fault tolerant self-triggered electronics is required for Data Acquisition (DAQ) system that can support high data rate (up to several TB/s). Basic readout chain for CBM consists of a front-end Application Specific Integrated Circuit (ASIC) also known as X-Y Time Energy Read-out (XYTER) ASIC, a radiation hardened high speed optical transceiver board with Gigabit Transceiver (GBTx) ASIC followed by a Data Processing Board (DPB) and First Level Event Selector Interface Board (FLIB). As the first step towards the development of the readout chain, FPGA prototypes of GBTx ASIC and XYTER ASIC also known as GBTx emulator and XYTER emulator are developed. GBTx chips are connected to the XYTER in the front end through Low Voltage Differential Signalling (LVDS) electrical line also known as E-link and in the back-end with DPB using optical fiber. In this work, an FPGA-based readout chain prototype comprising of XYTER emulator, GBTx emulator, and DPB is developed where control and configuration signal of XYTER will be sent from DPB through GBTx emulator. A Python script is written in the computer to generate the control information that will be transferred to DPB through Ethernet using IPBus protocol.

High speed fault tolerant secure communication for muon chamber using FPGA based GBTx emulator

The Compressed Baryonic Matter (CBM) experiment is a part of the Facility for Antiproton and Ion Research (FAIR) in Darmstadt at the GSI. The CBM experiment will investigate the highly compressed nuclear matter using nucleus-nucleus collisions. This experiment will examine lieavy-ion collisions in fixed target geometry and will be able to measure hadrons, electrons and muons. CBM requires precise time synchronization, compact hardware, radiation tolerance, self-triggered front-end electronics, efficient data aggregation schemes and capability to handle high data rate (up to several TB/s). As a part of the implementation of read out chain of Muon Cliamber(MUCH) [1] in India, we have tried to implement FPGA based emulator of GBTx in India. GBTx is a radiation tolerant ASIC that can be used to implement multipurpose high speed bidirectional optical links for high-energy physics (HEP) experiments and is developed by CERN. GBTx will be used in highly irradiated area and more prone to be affected by multi bit error. To mitigate this effect instead of single bit error correcting RS code we have used two bit error correcting (15, 7) BCH code. It will increase the redundancy which in turn increases the reliability of the coded data. So the coded data will be less prone to be affected by noise due to radiation. The data will go from detector to PC through multiple nodes through the communication channel. The computing resources are connected to a network which can be accessed by authorized person to prevent unauthorized data access which might happen by compromising the network security. Thus data encryption is essential. In order to make the data communication secure, advanced encryption standard [2] (AES - a symmetric key cryptography) and RSA [3], [4] (asymmetric key cryptography) are used after the channel coding. We have implemented GBTx emulator on two Xilinx Kintex-7 boards (KC705). One will act as transmitter and other will act as receiver and they are connected through optical fiber through small form-factor pluggable (SFP) port. We have tested the setup in the runtime environment using Xilinx Cliipscope Pro Analyzer. We also measure the resource utilization, throughput., power optimization of implemented design.