Sangeet Saha

Scheduling Dynamic Hard Real-Time Task Sets on Fully and Partially Reconfigurable Platforms

Reconfigurable systems are increasingly being employed in a large class of todays heterogeneous real-time embedded systems which often demand satisfaction of stringent timeliness constraints. However, executing a set of hard real-time applications on reconfigurable systems such that all timing constraints are satisfied while also allowing efficient resource utilization requires effective scheduling, mapping and admission control strategies. This letter presents methodologies for scheduling periodic hard real-time dynamic task sets on fully and partially reconfigurable field-programmable gate arrays (FPGAs). The floor of the FPGA is assumed to be statically equipartitioned into a set of homogeneous tiles (each of which act as individual processing elements or PEs) such that any arbitrary task of the given task set may be feasibly mapped into the area of a given tile. Experimental results reveal that the proposed algorithms are able to achieve high resource utilization with low task rejection rates over a variety of simulation scenarios.

Performance Evaluation of Multiple Image Binarization Algorithms Using Multiple Metrics on Standard Image Databases

The area of image binarization has matured to a significant extent in last few years. There has been multiple, well-defined metrics for quantitative performance estimation of the existing techniques for binarization. However, it stills remains a problem to benchmark one binarization technique with another as different metrics are used to establish the comparative edges of different binarization approaches. In this paper, an experimental work is reported that uses three different metrics for quantitative performance evaluation of seven binarization techniques applied on four different types of images: Arial, Texture, Degraded text and MRI. Based on visually and experimentally the most appropriate methods for binarization of images have been identified for each of the four classes under consideration. We have used standard image databases along with the archived reference images, as available, for experimental purpose.

Exploration of Multi-thread Processing on XILKERNEL for FPGA Based Embedded Systems

The present day FPGA (Field Programmable Gate Array) technology is capable to design high performance embedded systems based on its soft core (MicroBlaze) and hard core (PowerPC) processors, embedded memories and other IP cores. Embedded system design demands use of limited hardware resources with as minimum power as possible while providing higher throughput. One way to decrease the complexity of application is to use a thread-oriented design where a process is divided into a number of manageable pieces known as threads. Each thread is responsible for some part of the application, thus providing multitasking. Further, for real-time task execution we need to have an efficient RTOS (Real Time Operating System) infrastructure on FPGA. Deciding a particular scheduling algorithm for thread execution requires the knowledge of resource utilization for the specific scheduling policy. Hence, a proper exploration of the various thread scheduling algorithms in terms of resource utilization, for a given embedded platform is of much importance. The incorporation of XILKERNEL RTOS in FPGA is a latest facility. Though there exists a few research work on analyzing the resource requirement in multitasking scenario for a given embedded RTOS environment, our work on resource estimation for the various task scheduling policies using XILKERNEL is first of its kind. Implementation of real-time scheduling algorithm like RMS on XILKERNEL has also been endeavored, using OS virtualization, since it is not directly supported by the kernel of XILKERNEL.

Novel architecture of modular exponent on reconfigurable system

This paper proposes a single chip solution of the modulus exponent operation for FPGA based embedded system applications. Throughput and resource usage are the two most important issues in the design of embedded systems and the designers must need to choose appropriate hardware architecture to meet these requirements. There are two ways of hardware design namely parallel architecture and sequential architecture. Though sequential architecture has lesser throughput it is suitable for limited resource hardware domain like FPGA based systems. Parallel design may consume huge resources but it has better throughput compare to its sequential counterpart. In this paper, we have proposed the design and implementation of modulus exponent operation in three different ways namely single clock architecture, sequential architecture and a processor core based architecture. The proposed design is implemented and verified on Spartan 3E (XC3S500E-FG320) and Virtex-5, (XC5VLX110T-FF1136) FPGA system. We have used VHDL and SystemC for the various implementations in our work. The results show that our design is better in terms of execution speed and hardware utilization in comparison with the existing research work.

Co-Scheduling Persistent Periodic and Dynamic Aperiodic Real-Time Tasks on Reconfigurable Platforms

As task preemption/relocation with acceptably low overheads become a reality in todays reconfigurable FPGAs, they are starting to show bright prospects as platforms for executing performance critical task sets while allowing high resource utilization. Many performance sensitive real-time systems including those in automotive and avionics systems, chemical reactors, etc., often execute a set of persistent periodic safety critical control tasks along with dynamic event driven aperiodic tasks. This work presents a co-scheduling framework for the combined execution of such periodic and aperiodic real-time tasks on fully and run-time partially reconfigurable platforms. Specifically, we present an admission control strategy and preemptive scheduling methodology for dynamic aperiodic tasks in the presence of a set of persistent periodic tasks such that aperiodic task rejections may be minimized, thus resulting in high resource utilization. We used the 2D slotted area model where the floor of the FPGA is assumed to be statically equipartitioned into a set of tiles in which any arbitrary task may be feasibly mapped. The experimental results reveal that the proposed scheduling strategies are able to achieve high resource utilization with low task rejection rates over various simulation scenarios.

Task Allocation Strategies for FPGA Based Heterogeneous System on Chip

FPGA based heterogeneous System On Chips (SOCs) have become a prospective processing platform for modern performance-sensitive systems, like automotive, avionics, chemical reactor etc. In such system, “makespan” time minimization plays a crucial role to achieve higher throughput as well as performance efficiency and thus, efficient task allocation schemes are indeed essential. This paper presents two task allocation algorithms for such FPGA based heterogeneous SOCs. The first allocation strategy is based on well known “Branch and Bound” optimization technique. Secondly, we proposed a novel heuristic based allocation mechanism, TAMF (T ask A llocation M echanism for F PGA based heterogeneous SOC). The simulation based experimental results reveal that both the strategies are able to provide lower makespan time over various simulation scenarios with acceptable runtime overheads. Achieved simulation results are further tested through a validation, carried out on practical ZYNQ SOC platform using standard benchmark task sets.

Spatio-Temporal Scheduling of Preemptive Real-Time Tasks on Partially Reconfigurable Systems

Reconfigurable devices that promise to offer the twin benefits of flexibility as in general-purpose processors along with the efficiency of dedicated hardwares often provide a lucrative solution for many of today’s highly complex real-time embedded systems. However, online scheduling of dynamic hard real-time tasks on such systems with efficient resource utilization in terms of both space and time poses an enormously challenging problem. We attempt to solve this problem using a combined offline-online approach. The offline component generates and stores various optional feasible placement solutions for different sub-sets of tasks that may possibly be co-mapped together. Given a set of periodic preemptive real-time tasks that requires to be executed at runtime, the online scheduler first carries out an admission control procedure and then produces a schedule, which is guaranteed to meet all timing constraints provided it is spatially feasible to place designated subsets of these tasks at specified scheduling points within a future time interval. These feasibility checks are done and actual placement solutions are obtained through a low overhead search of the statically precomputed placement solutions. Based on this approach, we have proposed a periodic preemptive real-time scheduling methodology for runtime partially reconfigurable devices. Effectiveness of the proposed strategy has been verified through simulation based experiments and we observed that the strategy achieves high resource utilization with low task rejection rates over various simulation scenarios.