Rubem Dutra Ribeiro Fagundes

A Reed-Solomon Algorithm for FPGA Area Optimization in Space Applications

This work describes an algebraic based design strategy targeting area optimization in reconfigurable computer technology (FPGA). Area optimization is a major issue as smaller components allow for better system adaptation, which is an expected feature of reconfigurable systems for space applications. The approach is applied in the design stage of a component for the communications module of an on-board computer system. The chosen component is a Reed-Solomon encoder, which has been implemented using a Hardware Description Language (VHDL) according to CCSDS recommendations, and targeting an FPGA platform. The paper investigates traditional alternatives for the encoder implementation, introduces the algebraic theory behind the proposed approach, describes the design process and discusses the area figures reached by the new design.

Buffer depth and traffic influence on 3D NoCs performance

3D NoC-based architectures have emerged to reduce the network latency, the energy consumption and total area in comparison to 2D NoC topologies. However, they are characterized by various trade-offs with regard to the three dimensional structure and its performance specifications. In this paper, we present a 3D NoC mesh architecture called Lasio, whose latency and the throughput achieved, for both network and application, are evaluated considering two types of traffic patterns, varied buffer depth and a range of packet sizes. Cycle-accurate simulations demonstrated that there is a high impact of buffer depth and packet size on the NoC latency and on the application latency. Applying an appropriate buffer depth, for several sizes of packets, the application latency is reduced and throughput is increased.

Parallel Algebraic Approach of BCH Coding in VHDL

This work introduces an algebraic approach, using a Hardware Description Language (HDL) and shows that nowadays microelectronics technology could solve algebraic problems that were considered unsolvable using traditional sequential implementation forms as Berlekamp-Massey. An algebraic approach to implement Error Correcting Codes (ECC) is proposed, and implemented using a Hardware Description Language, specifically VHDL. The ECC designed for HDL algebraic implementation is Bose-Chaudhuri-Hocquenghem (BCH), that is one of the most important cyclic block codes. In this research work, we adopted n=63 and k=57, BCH(63,57) an usual configuration in many scientific communication systems as CCSDS telecommand systems of European Space Agency (ESA) and Agenda Espacial Brasileira (AEB). The achieved results clearly shows the main idea in our approach: to prove that an algebraic implementation is a far better approach, leading to an impressive efficiency, and much more suitable than any other sequential algorithm, even then the ones in a hardware version.

A new on-line robust approach to design noise-immune speech recognition systems

Hereafter, we present a new approach dealing to cope with the harmful effects of noise on speech recognition systems (SRS). This approach is oriented to hardware redundancy and it is essentially a modification of the classic Recovery Blocks scheme. When compared to conventional approaches using Fast Fourier Transform (FFT) and Hamming Code, the primary benefit of such a technique is to improve system performance when operating in real (i.e., noisy) environments. The second advantage is related to the considerably low complexity and reduced area overhead required for implementation. We implemented three full versions of the proposed algorithm: one running of a PC microcomputer, and a second one slightly modified to run on a TMS-320C67 Texas DSP microprocessor module. Both of them were described in the C language. Finally, a last implementation was prototyped on a HW-SW development environment based on the same Texas microprocessor and on the FLEX10K20 FPGA Altera Component.

Topological impact on latency and throughput: 2D versus 3D NoC comparison

NoC has emerged as as efficient communication infrastructure to fulfill the heavy communication requirements of several applications, which are implemented on MPSoC target architectures. 2D NoCs are natural choices of communication infrastructure for the majority of actual chip fabrication technologies. However, wire delay and power consumption are dramatically increasing even when using this kind of topology. In this sense, 3D NoC emerges as an improvement of 2D NoC aiming to reduce the length and number of global interconnections. This work explores architectural impacts of 2D and 3D NoC topologies on latency, throughput and network occupancy. We show that, in average, 3D topologies minimize 30% the application latency and increase 56% the packets throughput, when compared to 2D topologies. In addition, the paper explores the influence of the buffer length on communication architecture latency and on application latency, highlighting that when applying an appropriate buffer length the application latency in reduced up to 3.4 times for 2D topologies and 2.3 times for 3D topologies.

Experimental results of a recovery block scheme to handle noise in speech recognition systems

In this paper, we present the last improvements for a new approach to cope with noise that troubles speech recognition systems (SRS). This approach performs on-line monitoring and is oriented to hardware redundancy (it is essentially a modification of the classic recovery block scheme). When compared to conventional approaches using fast Fourier transforms (FFT) and Hamming code, the primary benefit of such a technique is to improve system performance when operating in real (i.e., noisy) environments. The second advantage is related to the considerably lower complexity and reduced area overhead required for implementation. We implemented three full versions of the proposed algorithm: one running on a PC microcomputer, and a second one slightly modified to run on a TMS-320C67 Texas DSP microprocessor module. Both of them were described in the C language. A last implementation was prototyped on a hardware/software development environment based on the same Texas microprocessor and on the FLEX10K20 FPGA Altera component.

Partitioning Algorithms Analysis for Heterogeneous NoC Based MPSoC

Several new applications have high complexity degree, requiring high processing rate and memory usage. Multiprocessor System-on-Chip (MPSoC) is a promising architecture to fulfill these requirements, due to its high parallelism that enables several tasks been executed at the same time. One problem in current heterogeneous MPSoC design is applications tasks partitioning aiming energy consumption minimization and load balance. In order to optimize partition problems, many algorithms have been applied to generate quality solutions. This work aims to analyze and compare stochastic and heuristic partitioning algorithms for obtaining low energy consumption and load balance when applied to tasks partitioning onto heterogeneous MPSoC.

Merging a DSP-Oriented Signal Integrity Technique and SW-Based Fault Handling Mechanisms to Ensure Reliable DSP Systems

Hereafter, we present an approach aiming to improve the reliability of digital signal processing (DSP) systems operating in real noisy (electromagnetic interference—EMI) environments. The approach is based on the coupling of two techniques: the “DSP-oriented signal integrity improvement” technique deals with increasing the signal-to-noise ratio (SNR) and is essentially a modification of the classic Recovery Blocks Scheme. The second technique, named “SW-based fault handling” aims to detect in real-time data- and control-flow faults throughout modifications of the processor code. When compared to conventional approaches using Fast Fourier Transform (FFT) and Hamming Code, the primary benefit of such an approach is to improve system reliability by means of a considerably low complexity, reasonably low performance degradation and, when implemented in hardware, with reduced area overhead. Aiming to illustrate the proposed approach, we implemented a HW/SW prototype to operate as a speech recognition system (SRS). This prototype was tested under a home-tailored EMI environment according to the IEC 61000-4-29 International Standard Normative. The obtained results indicate that the proposed approach can effectively improve the reliability of DSP systems operating in real noise (EMI) environments.

A new phonetic model for continuous speech recognition systems

The main goal of this work is to describe a new model for a large vocabulary continuous speech recognition system using a phonetic-phonological approach. This work proposes a statistical phonetic structure, applied at the phonetic-phonological level, to improve the speech recognition performance in systems with phonetic-phonological modeling. It is shown that the general likelihood scores are increased, indicating better recognition performance. This is due to the fact that the statistical phonetic structure leads to enhancement of some frequent phonetic combinations from the language itself. Such a structure should be considered as an additional knowledge base, containing information about the real language phonetic structure. Also this new phonetic-phonological approach should be strongly recommended for use in spontaneous speech recognition systems.