Ruey-Lue Wang

P-N double quantum well resonant interband tunneling diode with peak-to-valley current ratio of 144 at room temperature

The current-voltage characteristics of the P-N double quantum well resonant interband tunneling (RIT) diodes in InAlAs-InGaAs system have been improved in this letter. The peak-to-valley current ratio (PVCR) is as high as 144 at room temperature. As we know, this is the highest room temperature PVCR ever reported in any tunneling devices. Moreover, the influence of the central barrier thickness varying from 10 /spl Aring/ to 30 /spl Aring/ on the device characteristics is also studied.<<ETX>>

3~5 GHz Cascoded UWB Power Amplifier

In this paper, a two-stage cascaded power amplifier (PA), which consists of cascode topology, for ultrawideband (UWB) systems operating in the 3.1-4.8 GHz frequency range is presented. The shunt-shunt feedback is used to arrive at wideband matching. A three-section ladder output network is exploited to achieve excellent output match in a wideband fashion and to optimize the power performance. The PA is implemented by TSMC 0.18mm mixed signal/RF process. The measured results show the following performance: S21 of 20.7-dB, more than 10-dB input and output return loss, 5.8% maximum power-added-efficiency and 2.57dBm output P1dB with 15.57dB power gain at 3GHz

An Integrated CMOS Low Noise Amplifier for 3-5 GHz UWB Applications

For the ultra-wide-band communication applications, this work presents a two-stage topology to implement a low noise amplifier (LNA) based on the 0.18 um TSMC CMOS technology. We adopt the voltage-current resistor feedback and shunt-peaked circuit to obtain measurement results of maximum gain in 14.0 dB, noise figure below 5.25 dB, input and output reflection coefficients below -11dB within the bandwidth between 3 GHz to 5 GHz.

Flicker noise of GaN-based heterostructure field-effect transistors with Si-doped AlGaN carrier injection layer

Aluminum gallium nitride/gallium nitride (AlGaN/GaN) heterostructure field effect transistors (HFETs) with and without Si-doped AlGaN layer were fabricated and investigated. HFETs with the Si-doped AlGaN carrier-injection layer show better DC performance, and the transconductance is 150 mS/mm. However, the HFETs with Si-doped AlGaN layer present the deviation from the 1/f noise at low frequency. The Lorentz shape was observed in the noise spectrum. It suggests that traps might be more pronounced in this kind of structure. Therefore, the DC characteristics of HFETs can be improved by the insertion of Si-doped AlGaN layer, but it can result in more low-frequency noise with the carrier-injection layer.

A Nanocrystalline Silicon Surface-Passivation Layer on an HR-Si Substrate for RFICs

In this letter, a thin nanocrystalline silicon (nc-Si) layer grown by hot-wire chemical vapor deposition is used as a surface-passivation layer (SPL). The transmission loss αTL of coplanar waveguide lines on an oxide-coated high-resistivity silicon substrate with a 100-nm-thick nc-Si SPL is less than 1.05 dB/cm at frequencies up to 20 GHz. Furthermore, we found that the very thin nc-Si SPL is also greatly effective for reducing crosstalk noise and further enhancing the isolation characteristics of electrical circuits. Therefore, an nc-Si SPL is capable of providing good surface passivation for RF IC applications.

2–6GHz current-reused LNA with transformer-type inductors

In this work, a wideband CMOS LNA utilizing current-reused cascode topology is proposed. One series inductor and one shunt capacitor is inserted between two DC cascoded transistors in order that two transistors work as two cascaded common-source amplifiers under RF signals. Hence, higher power gain should be obtained. In general, more inductors are used to fulfill wideband matching and the current-reused topology. In this research, we designed an original wideband current-reused LNA previously. From the designed circuit structure, it can be found that three couples of inductors which are similar to center-tapped transformers. Hence, supply-feeding and matching inductors are combined into center-tapped transformers in order to save chip area.

Low Power Current-reused Voltage-Controlled Oscillator with Optimum Source Damping Resistors

In this paper, a low power current-reused voltage-controlled oscillator with source damping resistors is presented. It is designed by simulating optimum value of resistors. According to the simulation results, the output signals are symmetric and the 1/f3 region of the phase noise is reduced. The VCO1 is designed at 2.26 GHz. The measured phase noise at 100-kHz and 1-MHz offset frequencies are -101.87 and -121.66 dBc/Hz. With 1.8 V voltage supply, the power consumptions of the VCO is 1.62 mW. This circuit is fabricated by TSMC 0.18 um CMOS process.

Negative differential resistance of a delta-doping-induced double-barrier quantum-well diode at room temperature

A resonant-tunneling homojunction diode, which is a delta-doping-induced double-barrier quantum-well (D/sup 3/BQW) diode, is presented. The barrier uses the delta n/sup +/-i- delta p/sup +/-i- delta n/sup +/ structure. The current-voltage characteristics exhibit three sections of negative differential resistance (NDR) phenomena. At low bias, N-type NDR is demonstrated due to the resonant-tunneling effect. At higher bias, another N-type NDR appears due to the heating effect in the high electric field. As the external bias increases further, an S-type NDR is observed. This result is attributed to the impact ionization effect of thermionic electrons, and then trapping of holes in the maxima of the valence bands, resulting in barrier lowering and redistribution of voltage.<<ETX>>

Effect of thermal cycle on the interfacial antiferromagnetic spin configuration and exchange bias in Ni-Mn-Sb alloy

Effect of thermal cycle on the interfacial antiferromagnetic (AFM) spin configuration and exchange bias in Ni50Mn36Sb14 alloy has been investigated. The results indicate thermal cycle can induce further martensitic transition from part of arrested FM phase to AFM phase, leading to the reconstruction of interfacial antiferromagnetic spin configuration. The shape of hysteresis loops at 5 K after cooling back can be tuned from a single-shifted loop to a nearly symmetric double-shifted loop gradually accompanied with exchange bias field increasing to peak value and then decreasing. The evolutions can be illustrated intuitively by a simple AFM bidomain model.

Degeneration of CMOS Power Cells After Hot-Carrier and Load Mismatch Stresses

In this letter, we investigate the performance degradation of nMOS transistors due to hot-carrier effect and load impedance mismatch. The DC and radio-frequency characteristics, such as drain current, threshold voltage, transconductance, output power, power-added efficiency, etc., are affected under hot-carrier effect. With load impedance mismatch, the transistors experience the reflected power from load and increase the energy of hot carriers. This effect will make DC and power performances degenerate heavily. In this letter, device characteristics were measured at 5.2 GHz.