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Featured researches published by Cheng-Lin Huang.


international electron devices meeting | 2002

A 90 nm generation copper dual damascene technology with ALD TaN barrier

C. H. Peng; C. H. Hsieh; Cheng-Lin Huang; J. C. Lin; Minghsing Tsai; M. W. Lin; C. L. Chang; Winston Shue; Mong-Song Liang

As the device dimension continues to shrink, the need for a thinner barrier for copper has risen in order to meet the requirements for future device performance. The conventional barrier process by physical vapor deposition (PVD) has the limitation to achieve conformal step coverage across the dual damascene structure , and therefore would face a bottleneck when the thickness reduction is required. In this work, the atomic layer deposition (ALD) technique is applied for the TaN barrier process of a 90 nm generation copper dual damascene integration with low-k dielectrics of k=3.0. The ALD technique could not only provide a conformal step coverage on both trenches and vias, it could also allows reasonable thickness control for thickness of the order of 10 /spl Aring/. The integration results show that ALD TaN has promising electrical performance on sheet resistance, via resistance, and line-to-line leakage, and it also has superior reliability performance on electromigration, stress migration, and bias temperature test as compared with conventional PVD TaN.


Archive | 2006

Cleaning processes in the formation of integrated circuit interconnect structures

Cheng-Lin Huang; Ching-Hua Hsieh; Shau-Lin Shue


Archive | 2003

Method of barrier-less integration with copper alloy

Jing-Cheng Lin; Cheng-Lin Huang; Ching-Hua Hsieh; Shau-Lin Shue; Mong-Song Liang


Archive | 2003

Barrier free copper interconnect by multi-layer copper seed

Jing-Cheng Lin; Cheng-Lin Huang; Winston Shue; Mong-Song Liang


Archive | 2003

Method for simultaneous degas and baking in copper damascene process

Shing-Chyang Pan; Ching-Hua Hsieh; Jing-Cheng Lin; Hsien-Ming Lee; Cheng-Lin Huang; Shau-Lin Shue


Archive | 2003

Barrier-free copper interconnect

Jing-Cheng Lin; Cheng-Lin Huang; Winston Shue; Mong-Song Liang


Archive | 2005

Barrier structure for semiconductor devices

Chen-Hua Yu; Shing-Chyang Pan; Shau-Lin Shue; Ching-Hua Hsieh; Cheng-Lin Huang; Hsien-Ming Lee; Jing-Cheng Lin


Archive | 2012

Connector Design for Packaging Integrated Circuits

Chen-Hua Yu; Shin-puu Jeng; Shang-Yun Hou; Cheng-chieh Hsieh; Kuo-Ching Hsu; Ying-Ching Shih; Po-Hao Tsai; Chin-Fu Kao; Cheng-Lin Huang; Jing-Cheng Lin


Archive | 2011

Packaging Structures and Methods

Chen-Hua Yu; Shin-puu Jeng; Shang-Yun Hou; Kuo-Ching Hsu; Cheng-chieh Hsieh; Ying-Ching Shih; Po-Hao Tsai; Cheng-Lin Huang; Jing-Cheng Lin


Archive | 2008

Multi-Step Cu Seed Layer Formation for Improving Sidewall Coverage

Li-Lin Su; Shing-Chyang Pan; Cheng-Lin Huang; Ching-Hua Hsieh

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