Runiu Fang

Characteristics of Coupling Capacitance Between Signal-Ground TSVs Considering MOS Effect in Silicon Interposers

Along with extensive applications of through-silicon vias (TSVs) in 3-D systems, such as digital, logic, and memory modules, the accurate modeling of coupling capacitance between the TSVs is becoming indispensable to the signal integrity analysis of the system design. In this paper, the static characteristics of potential, electric field, and charges between signal-ground TSVs in a floating substrate are investigated, and accordingly, the effect of MOS capacitance on the coupling capacitance between signal and ground TSVs is accurately modeled and analyzed for both static and high-frequency situations. Furthermore, the impact of substrate admittance on the capacitance-voltage dependence is explored. Parametric studies are performed to study the effects of different physical and material parameters on the coupling capacitance, which include TSV radius, liner thickness, doping concentration, amount of oxide charges, and work function of TSV filling materials. Based on the proposed model, the nonlinear effect of the coupling capacitance on transient noise is examined and explained.

Development and characterization of a through-multilayer TSV integrated SRAM module

In this study, a stacked SRAM module with a built-in decoder was proposed with a through-multilayer TSV integration process. The through-multilayer TSVs provided data passages for all common signals, including the address bus, data bus, power, read and write control, which were redistributed at each individual chip, while the chip select signals were connected separately to the built-in decoder. Regarding this process, a novel double-layer spin coating technology was employed to prevent photoresist residue left inside TSVs, and the RDLs in this process could be fabricated using lift-off process prior to via filling. As a result, the front side CMP process was not necessary. A 10-layer through-multilayer TSV integration sample was successfully fabricated with this process. Preliminary testing results suggested that this process was promising for integration of memory chips with similar layout.

A 3D micro-channel cooling system embedded in LTCC packaging substrate

Micro fluidic channel embedded in LTCC packaging substrate is reported in IEEE-NEMS 2010 by our team, which showed that the micro channel can promise a great effect on heat-dissipating of the heat resource packaged in the LTCC substrate. Yet we find there is more room to intensify this effect. So we design a 3-D micro channel embedded in LTCC substrate which is not fabricated in one single layer but fabricated through multilayer substrate and constitute a channel circle surrounding the heat resource packaged inside. We accomplished some simulation on heat distribution, flow pressure and flow velocity field with commercial software FLUENT. This new structure can promise a much better effect on heat redistribution compared to single layer micro channel embedded in LTCC substrate. With this fluid channel the temperature of the outside package is tremendously cut down.

A wafer level through-stack-via integration process with one-time bottom-up copper filling

We reported a wafer level through-stack-via (TSV) integration approach for stacked memory module using onetime bottom-up copper filling. This bumpless TSV integration approach simplified the fabrication process and provided better reliability compared with solder based technologies. Silicon wafer with blind vias was first bonded to a carrier wafer face to face with pre-patterned BCB, and then thinned from backside to reveal the TSVs. The carrier wafer was coated with a release layer and a seed layer, which provided a uniform seed layer for bottom-up TSV filling and was easy to be debonded. A layer of copper RDL was pre-deposited on the silicon wafer before bonding, which enhanced the wettability of the sidewall of TSVs during bottom-up copper filling. More silicon wafers could be bonded and thinned in the same way. At last, one-time bottom-up TSV filling was performed and the carrier wafer was released. A 4-layer wafer stacking with TSVs of 173μm × 52μm has been successfully demonstrated with the thinnest wafer of 22μm. The electrical test results shown that this process had a significant yield improvement. The lowest resistance measured was 7.6mΩ with the yield of over 84% on the 4-inch wafer. This proposed TSV integration process was ready for stacked memory application.

Simulation-based investigation in effects of design parameters on electrical characters for a TSV-bump combination

The silicon industry has witnessed a half-century gallop of electronics. When technologies reached their limits, new technologies are budding out and prolong the unbreakable Moores Law. This time, Through Silicon Via (TSV) is considered the most promising technology trend in the next decade. In this paper, we study the electrical characters of a TSV-bump combination under the ground-signal-ground configuration. Effects of design parameters, including geometries and material parameters, on systematic electrical characteristics are investigated and concluded in terms of scatter (S) parameters by a 3D electromagnetic solver. To verify the simulated electrical performance, this paper proposes the equivalent electrical model of the GSG configuration consisting of RLCG parasitic elements. Analytical models are assigned to each parasitic component by employing classical equivalent circuit models of different types of transmission lines. Good agreement is achieved on S-parameters between the 3D electromagnetic solver and the proposed lumped circuit model in the frequency range of 0.1-20GHz.

Investigation of cooling performance of micro-channel structure embedded in LTCC substrate for 3D micro-system

The paper reports the design, fabrication and thermal property investigation of serpentine micro-channel structure embedded in Low Temperature Co-fired Ceramic (LTCC) substrate for thermal management of 3D micro-system. Serpentine micro-channel structure is about 2cm(length) × 2cm(width) × 2mm(thickness) in dimension and the micro-channel is about 200μm×200μm in its cross section. Infrared imaging is used to test temperature distribution of the whole LTCC substrate. Based on the test results, the cooling performance of the serpentine micro-channel is evaluated. With the present design of micro-channel, the experiment shows the maximum temperature of the substrate decreases from 85°C to 48°Cas the flow rate of deionized (DI) water through the micro-channel ranges from 0.59ml/min to 2.48ml/min. When the flow rate of DI water through micro-channel is increased with an increment of 0.5ml/min from 1.87ml/min, the decrease of maximum temperature of substrate is less than 2°C.

Noise coupling between through-silicon vias and active devices for 20/14-nm technology nodes

Although a through-silicon via (TSV) is widely used in three-dimensional integrated circuit systems, one of its major design challenges is noise coupling between TSVs and active devices. This paper investigates noise coupling between TSVs and active devices for 20/14-nm technology nodes. The effect of variations of structural parameters on noise coupling was examined using a three-dimensional full-wave electromagnetic field solver and its result was explained. Additionally, transient analysis on coupling noise was conducted with Synopsys TCAD. Furthermore, a combined strategy employing doped signal TSVs and ‘bare’ ground TSVs was proposed and compared with conventional signal/ground schemes. Demonstrated to improve noise isolation effectively, the proposed strategy is inherently advantageous to circuits of advanced technology nodes compared with other noise isolation schemes, for it demands no modification of the original circuit design, placement and routing.

Fast time domain crosstalk analysis of through silicon vias based on equivalent circuit model

Three-dimensional (3D) integration has been considered as the most promising method to overcome the interconnection bottleneck with through-silicon vias(TSVs) served as vertical signal channels. Three-dimensional integrated circuits (3D IC) meet the demands of high throughput, high scalability and low power consumption for future generation integrated circuits. Crosstalk is the dominant problem in signal integrity. While TSVs are bundled together as a cluster, the crosstalk coupling noise may lead to transmission errors. In this paper, we study several influencing factors of the crosstalk in the TSVs. Variations of space between two TSVs nets, different rise time of an attacking signal, various TSV stacking layers and three different types of communication models are modeled and analyzed to master their effect on the TSVs crosstalk. In order to verify the influence factors above, this paper proposes an equivalent electrical model of TSVs for crosstalk.

Electrical measurement and analysis of TSV/RDL for 3D integration

In this paper, electrical measurement and analysis of TSV/RDL is carried out, to evaluate the fabrication process and get a comprehensive understanding of electrical properties of TSV/RDL interconnect structures. DC resistance, leakage current and high frequency characterization are implemented. TSV shows a spreading distribution of DC resistance, with minimum of 4.3 mΩ. Leakage current of TSV reaches 150nA up to 30V without breakdown. Low substrate resistivity lowers the high frequency performance of TSV.

Investigation of a TSV-RDL in-line fault-diagnosis system and test methodology for wafer-level commercial production

In the first three quarters of 2013, semiconductor industry witnessed a great multiplication of 12-inch TSV wafers mounting to 1 million plus scale. Despite this increasing popularity, TSV technology suffers from high cost due to yield loss caused by process defects. Poor insulation and connectivity are the major problems for TSV and RDL(Re-Distribution Line) structures. Without a cost-effective test system and methodology, the faulty TSVs may be stacked onto good ones and therefore bring forth an increasing chip cost. In this paper, the leakage current and pathway resistance are characterized for TSV and RDL structures, and a two-step in-line test methodology was proposed to pinpoint these defects and screen out KGDs (Known Good Dies) on the wafer. Also, a wafer-level fault-diagnosis system based on the proposed technology was built, including a probe station, an analyzer and a controller software, and two test instances were carried out on the test system. The test results demonstrated the capability of the test methodology and system, and proved the potential feasibility of the methodology for volume pre-bond test.