Yuan Bian

Development and characterization of a through-multilayer TSV integrated SRAM module

In this study, a stacked SRAM module with a built-in decoder was proposed with a through-multilayer TSV integration process. The through-multilayer TSVs provided data passages for all common signals, including the address bus, data bus, power, read and write control, which were redistributed at each individual chip, while the chip select signals were connected separately to the built-in decoder. Regarding this process, a novel double-layer spin coating technology was employed to prevent photoresist residue left inside TSVs, and the RDLs in this process could be fabricated using lift-off process prior to via filling. As a result, the front side CMP process was not necessary. A 10-layer through-multilayer TSV integration sample was successfully fabricated with this process. Preliminary testing results suggested that this process was promising for integration of memory chips with similar layout.

A wafer level through-stack-via integration process with one-time bottom-up copper filling

We reported a wafer level through-stack-via (TSV) integration approach for stacked memory module using onetime bottom-up copper filling. This bumpless TSV integration approach simplified the fabrication process and provided better reliability compared with solder based technologies. Silicon wafer with blind vias was first bonded to a carrier wafer face to face with pre-patterned BCB, and then thinned from backside to reveal the TSVs. The carrier wafer was coated with a release layer and a seed layer, which provided a uniform seed layer for bottom-up TSV filling and was easy to be debonded. A layer of copper RDL was pre-deposited on the silicon wafer before bonding, which enhanced the wettability of the sidewall of TSVs during bottom-up copper filling. More silicon wafers could be bonded and thinned in the same way. At last, one-time bottom-up TSV filling was performed and the carrier wafer was released. A 4-layer wafer stacking with TSVs of 173μm × 52μm has been successfully demonstrated with the thinnest wafer of 22μm. The electrical test results shown that this process had a significant yield improvement. The lowest resistance measured was 7.6mΩ with the yield of over 84% on the 4-inch wafer. This proposed TSV integration process was ready for stacked memory application.

Electrical measurement and analysis of TSV/RDL for 3D integration

In this paper, electrical measurement and analysis of TSV/RDL is carried out, to evaluate the fabrication process and get a comprehensive understanding of electrical properties of TSV/RDL interconnect structures. DC resistance, leakage current and high frequency characterization are implemented. TSV shows a spreading distribution of DC resistance, with minimum of 4.3 mΩ. Leakage current of TSV reaches 150nA up to 30V without breakdown. Low substrate resistivity lowers the high frequency performance of TSV.

Understanding effect of additives in copper electroplating filling for through silicon via

3D integration with TSVs (Through Silicon Via) is emerging as a promising technology for the next generation integrated circuits. Copper electroplating is one of the key technologies to fabricate TSVs. In this paper, void-free TSV filling was achieved using methanesulfonic based electrolyte and mushroom-like copper overburden was used as bumps after tin deposition. Effect of additives and current density in copper electroplating nucleation and filling profile was investigated. An absorption-diffusion model was employed to explain the experimental results.

Parametric study, modeling of etching process and application for tapered through-silicon-via

Tapered TSV interconnection has begun used in CMOS Image Senor (CIS) and currently is penetrating its application in other areas, such as MEMS devices and Si Interposer. It helps relive the technical difficulties of conformal deposition of insulation layer and conducting layer and therefore its helpful for yield improvement and cost reduction. Besides that, it helps also relieve the stress accumulation at the opening of TSV which poses a potential threat to reliability. In this paper, parametric study of etching process for tapered TSV with SF6/C4F8/O2 will be carried out in an STS ICP etching machine. Interactions between the process parameters and TSV profile will be studied and TSV profile development versus time will be modeled for offering guidance for TSV profile design and its relative etching recipe design/optimization. Finally, in order to extend SF6/C4F8/O2 etching techniques capability in producing high depth, no sidewall bowing TSV, a manufacturing method featuring in a SF6/C4F8/O2 etching followed by a BOSCH process will be proposed, and recipe design/optimization and its verification for a designed tapered TSV will be detailed.

Effect of additives on copper electroplating profile for TSV filling

3D integration with TSVs is emerging as a promising technology for the next generation integrated circuits. TSV filling is a critical process in TSV fabrication and has direct effect on electrical performance of TSVs. In this paper, we mainly focus on effect of additives used in methanesulfonic based solution on copper electroplating filling. Numerical simulation based on an absorption-diffusion model has been carried out with electrochemical data. TSV filling experiment results with different additive concentrations are presented and void-free TSV filling has been achieved.

Fabrication and Traceable Quality Evaluation of Fine Pitch TSV with Self-Integrated Micro Heater and Thermocouple

As the pitch of TSVs shrinks down, electrical characteristics of TSV become more complicated and mechanical stress becomes a critical issue. The objective of this paper is to study the electrical and mechanical characteristics of fine pitch TSV. The features are that the fine pitch TSV samples are fabricated with self-integrated micro heater and thermocouple, which are integrated to act as the hot spot and to online monitor the temperature variation during test respectively. X-ray inspection is carried out to verify the internal filling quality of fine pitch TSV electroplating. The appearance of micro heater and thermocouple are observed by 3D profiler. The cross section of this fine pitch TSV is observed by scanning electron microscope. The yield of all test structure turns out to be 99.50% at the laboratory level. The values of Kelvin resistance in test structure is measured by changing the temperature of self-integrated micro heater. Thermo-mechanical stress is qualitative characterized by an infrared photo-elastic system during thermal shock which demonstrates that around of the failure TSV is under more stress, through which we can evaluate the quality of fine pitch TSV fast and accurately.

Chemical-mechanical polishing of bulk tungsten substrate

Bulk tungsten is very promising for packaging and micro-devices for its high strength, radiation resistance, high melting point and conductivity. In this paper, chemical mechanical polishing of bulk tungsten substrate was carried out. A 4 inch tungsten wafer was polished at the optimized condition with an average surface roughness of 4.63nm achieved. Bulk tungsten applications in packaging and micro-devices will be expanded.

Process development of a stacked chip module with TSV interconnection

In this paper, a novel 3D integration process named Via-Backside-Release process, abbreviated as VBR process, is proposed and technical issues are addressed. With VBR process, theres no need of removal process of copper overburden due to the filling of TSV by copper electroplating, and no individual unit process for producing Cu/Sn microbumps. In order to verify the feasibility of VBR process, a test run is carried out and a four-layer of chip module is demonstrated.

Development of a through-stack-via integrated SRAM module

In this paper, a through-stack-via integration process for SRAM module was developed using wafer level pre-patterned BCB bonding. A SRAM module with a built-in decoder has been designed according to this integration process. TSVs passed through all stacked SRAM chips and common signals, including address bus, data bus, power, write and read control, were connected to the same TSV using RDL. The chip select signals are individually connected to the built-in decoder. RDL was fabricated using lift-off process prior to wafer bonding and via filling. Double-layer spin coating technology was employed to prevent photoresist residues left in TSVs. With pre-patterned BCB adhesive bonding, a bottom-up TSV filling features as the last step, which eliminates the traditional solder bumping, flip chip bonding and underfill filling processes. Preliminary results have shown that this process is promising for integration of memory chips with similar layout.