Ryan Huang

Endurance enhancement of Cu-oxide based resistive switching memory with Al top electrode

We investigated the switching performance of Cu-oxide films with Al, Pt, and Ti electrodes. Compared with Pt electrode, the Al electrode shows better stability, preferable endurance, and larger resistance ratio. An interface AlOx layer is detected by transmission electron microscopy and Auger electron spectroscopy. This layer can strongly affect the movement of oxygen vacancies. However, the sample with pure Ti electrode almost has no switching characteristics. Ti/TiN electrode with thin Ti exhibits good switching behavior. The thickness control of Ti layer is quite critical. So we suggest that the oxygen diffusion in electrode is another important factor for switching performance.We investigated the switching performance of Cu-oxide films with Al, Pt, and Ti electrodes. Compared with Pt electrode, the Al electrode shows better stability, preferable endurance, and larger resistance ratio. An interface AlOx layer is detected by transmission electron microscopy and Auger electron spectroscopy. This layer can strongly affect the movement of oxygen vacancies. However, the sample with pure Ti electrode almost has no switching characteristics. Ti/TiN electrode with thin Ti exhibits good switching behavior. The thickness control of Ti layer is quite critical. So we suggest that the oxygen diffusion in electrode is another important factor for switching performance.

A novel Cu x Si y O resistive memory in logic technology with excellent data retention and resistance distribution for embedded applications

A new Cu<inf>x</inf>Si<inf>y</inf>O resistive memory, which is different from Cu-doped SiO<inf>2</inf> or CuxO binary oxide, is integrated successfully in standard logic technology for the first time. Key breakthrough is that data retention (10 years@ 150°C), resistance distribution (with 50x window@125 °C ) and disturbance immunity significantly improved with integration simplicity advantage, as demonstrated on a 1Mb test chip. The activation energy of Cu vacancy migration in Cu<inf>x</inf>Si<inf>y</inf>O increases by 5 times than that in Cu<inf>x</inf>O, giving rise to the great performance improvement. The solution is promising for both high density and low cost embedded nonvolatile memory (NVM) applications.

A Logic Resistive Memory Chip for Embedded Key Storage With Physical Security

A 64-kB logic resistive random access memory (RRAM) chip for physically secure key storage is presented. The chip has security features of resisting fully invasive attacks such as deprocessing and microscopy observation, resisting side-channel attacks by providing symmetrical power and timing read signals, resisting malicious writing by a reduced write protection scheme with feedback, and resisting data interception attack across pin boundary by the ability of on-chip integration with logic platform. The chip is fabricated in a 0.13-μm standard logic process and implemented as the key storage for a demonstrative information security platform with a MIPS-based cryptoprocessor. Experiments of reverse engineering and mechanism investigation proved the fully invasive attack-resistant features, and experiments emulating side-channel attacks revealed no difference between 0 and 1. Experiments also showed that the information security platform could correctly encrypt and decrypt with the RRAM key storage. The proposed chip has obvious advantage on area, power, and security features for embedded key storage compared with its Antifuse counterpart.

A 0.13µm 8Mb logic based Cu x Si y O resistive memory with self-adaptive yield enhancement and operation power reduction

A 0.13μm 8Mb CuxSiyO resistive memory test macro with 20F2 cell size is developed based on logic process for the first time. Smart and adaptive assist write and read circuit are proposed and verified in order to fix yield and power consumption issues from large write speed and high temperature resistance variation. SAWM (self-adaptive write mode) helps to enlarge Roff/Ron window from 8X to 24X at room temperature. The reset bit yield is improved from 61.5% to 100% and large power consumption is eliminated after set success. SARM (Self-adaptive read mode) improves read bit yield from 98% to 100% at 125°C. The typical access time of on-pitch voltage sensing SA(sense amplifier) is 21ns and high bandwidth throughput is supported.

Fast step-down set algorithm of resistive switching memory with low programming energy and significant reliability improvement

We propose an asymmetric write algorithm of step-down set/step-up reset without verify for the first time. The demonstration is carried out on a 128Kb test macro of AlO_x/WO_x bi-layer ReRAM fabricated based on 0.18μm logic process. The set and reset energy per bit are reduced by 34% and 20% respectively. The set and reset access time decrease by 54% and 32% respectively. The mean value of endurance distribution is improved by 2 orders of magnitude from 10⁷ to 10⁹. R_on and R_off retention failure rate is reduced by 88% and 71% respectively. R_off/R_on window enlarges from 25× to 180×. The reliability improvements are attributed to refinement of CF shape and size by the step-down set algorithm.

A low cost and high reliability true random number generator based on resistive random access memory

A high reliability system for the generation of truly random numbers, based on Resistive Random Access Memory (RRAM) has been proposed. The circuit is using the random telegraph noise (RTN) in RRAM cell as a source of noise to force more jitter into the oscillators. Because these RTN signals from the RRAM cells are much larger than that in the MOSFET and thermal noise in a resistor, then the preamplifier is not required. A prototype chip has been fabricated in SMIC 0.18um standard CMOS logic process. The test results show that the features of the proposed true random number generator (TRNG) fulfill the NIST tests for randomness.

A Systematic Investigation of TiN/CuxO/Cu RRAM with Long Retention and Excellent Thermal Stability

The long retention, more than 10 years at 85degC, and excellent thermal reliability memory of TiN-Cu x O-Cu (with TiN cap layer as top electrode) is reported. TiN cap layer results in more stable reset from low resistance state (LRS) to high resistance state (HRS) under positive pulse and SET under negative pulse, which is beneficial for providing large programming current or voltage on the resistive random access memory (RRAM) resistor connected in series with a select transistor. Results show that the structure of TiN-Cu x O-Cu with its compatibility to CMOS technology appears a promising memory device for embedded application.

Dual Resistive Switching Characteristics in CuxSiyO Resistive Memory

Bipolar and unipolar resistive switching was alternatively obtained in CuxSiyO resistive memory by controlling the voltage polarity and current compliance during the electroforming process. The dual switching modes showed significant differences in electrical parameters, such as switching voltage, gradual/sharp RESET, and ON/OFF resistance. Analyses of current–voltage (I–V) curve fitting and temperature coefficient relationship (TCR) indicated that the conductive filament was composed of vacancies in bipolar devices but metallic Cu in unipolar devices. A possible conduction model was sketched to interpret the coexistence of dual resistive switching.

Low-Power Variation-Tolerant Nonvolatile Lookup Table Design

Emerging nonvolatile memories (NVMs), such as MRAM, PRAM, and RRAM, have been widely investigated to replace SRAM as the configuration bits in field-programmable gate arrays (FPGAs) for high security and instant power ON. However, the variations inherent in NVMs and advanced logic process bring reliability issue to FPGAs. This brief introduces a low-power variation-tolerant nonvolatile lookup table (nvLUT) circuit to overcome the reliability issue. Because of large ROFF/RON, 1T1R RRAM cell provides sufficient sense margin as a configuration bit and a reference resistor. A single-stage sense amplifier with voltage clamp is employed to reduce the power and area without impairing the reliability. Matched reference path is proposed to reduce the parasitic RC mismatch for reliable sensing. Evaluation shows that 22% reduction in delay, 38% reduction in power, and the tolerance of variations of 2.5× typical RON or ROFF in reliability are achieved for proposed nvLUT with six inputs.

A 2Mb ReRAM with two bits error correction codes circuit for high reliability application

A 2-Mb resistive random access memory (ReRAM) is demonstrated in 0.13-um CMOS logic process. The paper describes the cell, chip architecture, and circuit techniques to ReRAM design; The 2-Mb ReRAM chip features three circuit technologies to improve the memory yield and performance: 1) for a better endurance and resistance distribution a ramped current pulse write driver (RCPWD) circuit is designed, 2) considering process variation and verify used, a programmable reference sense amplifier (PRSA) for stable read operation is designed, and 3) for improving the yield and reliability for some special application, a double error correction codes (DEC) circuit is introduced for yield requirement of high reliability applications.