Xiaoyong Xue

A 3D RRAM using stackable 1TXR memory cell for high density application

This paper reports a novel 3D RRAM concept using stackable multi-layer 1TXR memory cell structure for future high density application. Using an 8-layer metal of stacked 1TXR (X=64) as an example, the density is over 260% higher than that of the conventional single layer 1T1R structure. Corresponding operation algorithm is put forward for the first time, which can inhibit mis-write and mis-read caused by sneaking current and reduce power consumption.

Novel RRAM programming technology for instant-on and high-security FPGAs

This paper introduces a novel RRAM programming technology to improve the security and shorten the startup time of FPGAs. A 9T2R nonvolatile SRAM (nvSRAM) cell is comprised of two 1T1R RRAM cells and a standard 6T SRAM cell on a single die by integrating the RRAM technology into the standard logic process. The 9T2R cell stores the configuration bit in the two 1T1R cells in complementary style and can quicky read it into the SRAM cell in less than 300 ps at power-on. Besides, the proposed RRAM programming technology excels SRAM in dynamic reconfiguration for less interrupt time or small area overhead. A testchip of a 2-input LUT with the proposed RRAM programming technology has been demonstated in 0.13µm logic technology.

A Logic Resistive Memory Chip for Embedded Key Storage With Physical Security

A 64-kB logic resistive random access memory (RRAM) chip for physically secure key storage is presented. The chip has security features of resisting fully invasive attacks such as deprocessing and microscopy observation, resisting side-channel attacks by providing symmetrical power and timing read signals, resisting malicious writing by a reduced write protection scheme with feedback, and resisting data interception attack across pin boundary by the ability of on-chip integration with logic platform. The chip is fabricated in a 0.13-μm standard logic process and implemented as the key storage for a demonstrative information security platform with a MIPS-based cryptoprocessor. Experiments of reverse engineering and mechanism investigation proved the fully invasive attack-resistant features, and experiments emulating side-channel attacks revealed no difference between 0 and 1. Experiments also showed that the information security platform could correctly encrypt and decrypt with the RRAM key storage. The proposed chip has obvious advantage on area, power, and security features for embedded key storage compared with its Antifuse counterpart.

A 0.13µm 8Mb logic based Cu x Si y O resistive memory with self-adaptive yield enhancement and operation power reduction

A 0.13μm 8Mb CuxSiyO resistive memory test macro with 20F2 cell size is developed based on logic process for the first time. Smart and adaptive assist write and read circuit are proposed and verified in order to fix yield and power consumption issues from large write speed and high temperature resistance variation. SAWM (self-adaptive write mode) helps to enlarge Roff/Ron window from 8X to 24X at room temperature. The reset bit yield is improved from 61.5% to 100% and large power consumption is eliminated after set success. SARM (Self-adaptive read mode) improves read bit yield from 98% to 100% at 125°C. The typical access time of on-pitch voltage sensing SA(sense amplifier) is 21ns and high bandwidth throughput is supported.

Fast step-down set algorithm of resistive switching memory with low programming energy and significant reliability improvement

We propose an asymmetric write algorithm of step-down set/step-up reset without verify for the first time. The demonstration is carried out on a 128Kb test macro of AlO_x/WO_x bi-layer ReRAM fabricated based on 0.18μm logic process. The set and reset energy per bit are reduced by 34% and 20% respectively. The set and reset access time decrease by 54% and 32% respectively. The mean value of endurance distribution is improved by 2 orders of magnitude from 10⁷ to 10⁹. R_on and R_off retention failure rate is reduced by 88% and 71% respectively. R_off/R_on window enlarges from 25× to 180×. The reliability improvements are attributed to refinement of CF shape and size by the step-down set algorithm.

A low cost and high reliability true random number generator based on resistive random access memory

A high reliability system for the generation of truly random numbers, based on Resistive Random Access Memory (RRAM) has been proposed. The circuit is using the random telegraph noise (RTN) in RRAM cell as a source of noise to force more jitter into the oscillators. Because these RTN signals from the RRAM cells are much larger than that in the MOSFET and thermal noise in a resistor, then the preamplifier is not required. A prototype chip has been fabricated in SMIC 0.18um standard CMOS logic process. The test results show that the features of the proposed true random number generator (TRNG) fulfill the NIST tests for randomness.

Nonvolatile SRAM cell based on Cu x O

A nonvolatile static random access memory (NVSRAM) cell with two back-up CuxO memory devices is proposed in this paper. The manufacturing process is compatible with the standard CMOS process. By adopting a dynamic supply voltage scheme, the proposed cell can work correctly in four different operation modes. Compared with the standard SRAM cell, the proposed cell offers non-volatile storage which allows the unused blocks of SRAM to be powered down to save energy.

Novel 3D horizontal RRAM architecture with isolation cell structure for sneak current depression

Both 3D Vertical RRAM (VRRAM) and 3D Horizontal RRAM (HRRAM) architecture suffer from the issue of serious sneaking current, which leads to read or write disturbance and unacceptable power consumption waste, severely limiting its spatial stack-ability. In this work, the power consumption caused by sneaking current is separated out from the total set power consumption in HRRAM architecture. Then isolation cell structure is proposed to suppress the sneaking current. Simulation results show that total power consumption is reduced by about 30% with our proposed structure. Meanwhile, disturbance and read margin also show improvements.

Low-Power Variation-Tolerant Nonvolatile Lookup Table Design

Emerging nonvolatile memories (NVMs), such as MRAM, PRAM, and RRAM, have been widely investigated to replace SRAM as the configuration bits in field-programmable gate arrays (FPGAs) for high security and instant power ON. However, the variations inherent in NVMs and advanced logic process bring reliability issue to FPGAs. This brief introduces a low-power variation-tolerant nonvolatile lookup table (nvLUT) circuit to overcome the reliability issue. Because of large ROFF/RON, 1T1R RRAM cell provides sufficient sense margin as a configuration bit and a reference resistor. A single-stage sense amplifier with voltage clamp is employed to reduce the power and area without impairing the reliability. Matched reference path is proposed to reduce the parasitic RC mismatch for reliable sensing. Evaluation shows that 22% reduction in delay, 38% reduction in power, and the tolerance of variations of 2.5× typical RON or ROFF in reliability are achieved for proposed nvLUT with six inputs.

3D vertical RRAM architecture and operation algorithms with effective IR-drop suppressing and anti-disturbance

We propose co-optimization of VRRAM cell structure and array architecture as well as IR-drop-aware read/write algorithms to overcome issues of disturbance and IR drop from long wire. A bi-directional diode (2D) access device is combined with one resistor to form 2D1R cell. A dummy reference plane is inserted into array to set up the same IR drop path of reference cell with that of selected cell. Consequently, the same IR drop effect can be cancelled during read. The model for disturbance analysis is put forward. Voltage dropped on un-selected bit lines is the key parameter to suppress set disturbance. Set disturbance is significantly suppressed even when number of RRAM layers increases to 64. Set voltage has to meet corresponding requirements in order to minimize the disturbance risk.