Qingtian Zou

Linear Scaling of Reset Current Down to 22-nm Node for a Novel

The relationship between low resistance (<i>R</i>_on) and cell size (from 40 nm to 100 μm) is systematically investigated using a 1-Mb Cu<i>x</i>Si<i>y</i>O resistive RAM (RRAM) array. To our knowledge, this is the first study to attempt such an endeavor. Spacer pattern technology is employed to obtain a small cell size on the basis of a 0.13-μm standard logic process. <i>R</i>_on exhibits minimal change at 100 μm to 90 nm of RRAM size. However, it quadratically increases at 90 to 40 nm. The reset current, which is highly dependent on <i>R</i>_on, is linearly reduced fivefold in accordance with cell size, thereby improving overall power reduction and cell size scaling. The <i>R</i>_on dependence on cell size can be well explained by the dendritelike conductive filament model.

\hbox{Cu}_{x}\hbox{Si}_{y}\hbox{O}

A 64-kB logic resistive random access memory (RRAM) chip for physically secure key storage is presented. The chip has security features of resisting fully invasive attacks such as deprocessing and microscopy observation, resisting side-channel attacks by providing symmetrical power and timing read signals, resisting malicious writing by a reduced write protection scheme with feedback, and resisting data interception attack across pin boundary by the ability of on-chip integration with logic platform. The chip is fabricated in a 0.13-μm standard logic process and implemented as the key storage for a demonstrative information security platform with a MIPS-based cryptoprocessor. Experiments of reverse engineering and mechanism investigation proved the fully invasive attack-resistant features, and experiments emulating side-channel attacks revealed no difference between 0 and 1. Experiments also showed that the information security platform could correctly encrypt and decrypt with the RRAM key storage. The proposed chip has obvious advantage on area, power, and security features for embedded key storage compared with its Antifuse counterpart.

RRAM

We propose an asymmetric write algorithm of step-down set/step-up reset without verify for the first time. The demonstration is carried out on a 128Kb test macro of AlO_x/WO_x bi-layer ReRAM fabricated based on 0.18μm logic process. The set and reset energy per bit are reduced by 34% and 20% respectively. The set and reset access time decrease by 54% and 32% respectively. The mean value of endurance distribution is improved by 2 orders of magnitude from 10⁷ to 10⁹. R_on and R_off retention failure rate is reduced by 88% and 71% respectively. R_off/R_on window enlarges from 25× to 180×. The reliability improvements are attributed to refinement of CF shape and size by the step-down set algorithm.

A Logic Resistive Memory Chip for Embedded Key Storage With Physical Security

Bipolar and unipolar resistive switching was alternatively obtained in CuxSiyO resistive memory by controlling the voltage polarity and current compliance during the electroforming process. The dual switching modes showed significant differences in electrical parameters, such as switching voltage, gradual/sharp RESET, and ON/OFF resistance. Analyses of current–voltage (I–V) curve fitting and temperature coefficient relationship (TCR) indicated that the conductive filament was composed of vacancies in bipolar devices but metallic Cu in unipolar devices. A possible conduction model was sketched to interpret the coexistence of dual resistive switching.

Fast step-down set algorithm of resistive switching memory with low programming energy and significant reliability improvement

Emerging nonvolatile memories (NVMs), such as MRAM, PRAM, and RRAM, have been widely investigated to replace SRAM as the configuration bits in field-programmable gate arrays (FPGAs) for high security and instant power ON. However, the variations inherent in NVMs and advanced logic process bring reliability issue to FPGAs. This brief introduces a low-power variation-tolerant nonvolatile lookup table (nvLUT) circuit to overcome the reliability issue. Because of large ROFF/RON, 1T1R RRAM cell provides sufficient sense margin as a configuration bit and a reference resistor. A single-stage sense amplifier with voltage clamp is employed to reduce the power and area without impairing the reliability. Matched reference path is proposed to reduce the parasitic RC mismatch for reliable sensing. Evaluation shows that 22% reduction in delay, 38% reduction in power, and the tolerance of variations of 2.5× typical RON or ROFF in reliability are achieved for proposed nvLUT with six inputs.

Dual Resistive Switching Characteristics in CuxSiyO Resistive Memory

A high performance 2T gain cell memory device is demonstrated for the first time in 0.13μm CMOS technology. A novel asymmetric source and drain doping profile combined with high threshold voltage (Vt) scheme for the write transistor is introduced to reduce the cell leakage and then improve data retention characteristics. Experimental results show a data retention of 698μs @85°C with 99.9% yield, which proves that the proposed 2T gain cell may be a very promising candidate for low cost and high density eDRAM application.

Low-Power Variation-Tolerant Nonvolatile Lookup Table Design

A new soft forming algorithm, proposed in this letter, is demonstrated to improve endurance of an AlOx/WOy bilayer resistive random access memory array by two orders of magnitude. Relative to the conventional strong forming algorithm, soft forming creates a thinner conductive filament (CF) by applying voltage pulses that have narrower widths and lower amplitude. The mechanism can be explained by a CF model. soft forming algorithm is beneficial to form a thinner CF, which contains more movable oxygen vacancies (Vo) than that is formed by strong forming method. The rupture of thinner CF requires less movable oxygen ions (O2-). Consequently, exhaustion of movable Vo/O2- slows down and the number of set/reset cycles is increased, which improves endurance of the array.

Novel 2T gain cell with enhanced retention time for embedded DRAM application

Three techniques are proposed and verified on a logic-based 128kb embedded DRAM macro. Novel 2T gain cell of asymmetric junction increases data retention by 21X. Dynamically adaptive staggered refresh achieves zero data availability penalty and improves yield significantly. 60% smaller cell size than 6T SRAM and 25-30% refresh power reduction are obtained.

Endurance Enhancement by Soft Forming Algorithm on AlO x /WO y Resistive Switching Memory Array

A high performance bulk floating body memory device is demonstrated in this work. Experimental results show a data retention of 1.89s and a initial memory window over 60μA@85°C, which are excellent features for eDRAM application. A novel read method based on parasitic BJT effect is introduced to improve device performance. The impact of process parameters is investigated and P well doping is found to be the key factor. The scaling potential of the proposed read scheme is also evaluated by the measurement of devices with several (W/L, Tox) combinations.