Ryo Hattori

1 W Ku-band AlGaAs/GaAs power HBTs with 72% peak power-added efficiency

High power and high-efficiency multi-finger HBTs (heterojunction bipolar transistors) have been successfully realized at Ku-band by using emitter ballasting resistors and a PHS (plated heat sink) structure. An output power of 1 W with power added efficiency (PAE) of 72% at 12 GHz has been achieved from a ten-finger HBT with the total emitter size of 300 /spl mu/m/sup 2/. 72% PAE with the output power density of 5.0 W/mm is the best performance in the HBTs of which the output powers are more than 1 W at Ku-band.<<ETX>>

K-band high gain and high reliability GaAs power FET with sub-half micron WSi/Au T-shaped gate

We have developed a K-band GaAs power MESFET with 0.35 /spl mu/m WSi/Au T-shaped gate structure. This structure has been realized by forming a SiO/sub 2/ sidewall at both sides of recess, so the gate length is easily reduced to sub-half micron. A gate-to-drain breakdown voltage (Vgdo) of over 15 V, which depends strongly on the distance between gate edge and recess edge, is achieved when the sidewall width is adjusted to be more than 0.25 /spl mu/m. The 900 /spl mu/m gate-width FET has delivered an output power at 1 dB gain-compression point of 27.2 dBm with a linear gain of 9.5 dB at 18 GHz. An excellent mean time to failure (MTTF) of over 3E7 hours at Tch=125/spl deg/C has been obtained for the WSi/Au gate FET.

Stability analysis and layout design of an internally stabilized multi-finger FET for high-power base station amplifiers

A high-power, discrete, and internally-matched FET, such as for use in base station amplifiers, consists of lots of gate fingers to realize a very large periphery. It is well-known that many active devices combined in parallel likely form many closed loops and cause odd mode oscillation. However, stability analysis among FET fingers is usually complex, because of the existence of lots of active nodes. In this paper, novel internally stabilized multi-finger FET layout methodology with a branched gate feed structure is proposed, to stabilize among gate fingers without increasing the occupied layout area of the FET. The feature of this layout is that the branched gate feed structure, which can be fabricated without any extra processing step, functions as a resistor to isolate each FET cell. Stability analysis and layout design were achieved by using the NDF (Normalized Determinant Function) evaluation technique, which can deal with lots of active nodes. In an experiment for a GaAs FET of 134 mm gate width with 168 gate fingers, this stability analysis precisely predicted an oscillation frequency of the FET having multiple closed loops. The new approach presented here on the gate feed structure effectively suppressed odd mode oscillation.

Three-dimensional modeling of thermal flow in multi-finger high power HBTs

Three-dimensional modeling of thermal flow in multi-finger HBTs has been investigated with thermal network method to find out the optimal structure which can effectively reduce the junction temperature uniformly in whole fingers under the high power operation. Thermal cross-talk effects and temperature distribution in a finger or between the fingers are examined. The HBT structure with emitter air-bridge connected to via hole is proposed as an optimal structure. The estimation accuracy of the calculation was confirmed from the good agreement between the calculation result and the measured value of the thermal resistance in HBT with the emitter air-bridge structure.<<ETX>>