Kazuki Fukuoka

A 1.92 μs-wake-up time thick-gate-oxide power switch technique for ultra low-power single-chip mobile processors

A technique for controlling rush current and wake-up time of thick-gate-oxide power switches is described. Suppressing the variation of rush current on PVT allows shorter wake-up times, which can reduce leakage currents in a mobile processor. Wake-up takes 1.92 μs and leakage current is reduced by 96.9% in an application CPU domain. Probing the rush current indicated accurate control by the technique.

A 28 nm High-k/MG Heterogeneous Multi-Core Mobile Application Processor With 2 GHz Cores and Low-Power 1 GHz Cores

This paper presents power management and low power techniques of our heterogeneous quad/octa-core mobile application processor (AP). This AP has a combination of high-performance 2 GHz cores and energy-efficient 1 GHz cores. The maximum performance in the octa-core configuration is 35,600 DMIPS. The key design highlights are as follows. 1) Using a dedicated PLL and H-tree clock in the high-performance CPU achieves both 2 GHz operation and reduced dynamic power. 2) A low-leakage SRAM in a 28 nm HPM process is used and the leakage current of the peripheral circuits of the SRAM macro is optimized via multiple threshold voltages (Vt) and gate lengths (Lg), resulting in 24% leakage reduction of L1 cache. 3) The effects of process and voltage variations are accurately corrected by an on-chip process sensor and direct sensing of the voltage in the power mesh of the chip. 20% dynamic power reduction, 29% leakage power reduction and 40 mV improvement of minimum operation voltage are achieved. 4) An enhanced CPU clock control mechanism is employed, which uses an on-chip delay sensor to reduce AC voltage drop. 5) The heterogeneous CPU architecture maintains high performance even during thermal throttling.

4.5 A 16nm FinFET heterogeneous nona-core SoC complying with ISO26262 ASIL-B: Achieving 10−7 random hardware failures per hour reliability

The role of car information systems (commonly referred to as car infotainment) is expanding from dedicated navigation systems to joint car-cockpit systems, including the dashboard meter, telematics for the internet/cloud, and advanced driver-assistance systems (ADASs), such as adaptive cruise control and a pre-crash safety system. The expanding role for car information systems requires higher computational performance, but also safety mechanisms which prevent serious accidents. This paper presents an SoC for the next generation of car infotainment, achieving high performance powered by nine heterogeneous CPUs and a high level of safety, complying with ISO26262 ASIL-B. It has two key features: 1) Run-time test for functional safety, which can detect wear-out faults, such as random fault, time-dependent dielectric breakdown, and electromigration; 2) A killer-droop (critical voltage droop) monitor with droop prediction, which can avoid a delay fault caused by voltage droop.

A 28nm High-κ metal-gate single-chip communications processor with 1.5GHz dual-core application processor and LTE/HSPA+-capable baseband processor

The increase in the use and number of smartphone devices is causing heavy data traffic volumes on existing 3G mobile wireless networks. LTE, often referred to as 4G, offers true mobile broadband. It is a new network and access technology that provides new spectrum resources, much increased spectral efficiency, higher throughputs (150Mb/s with higher rates to come), at lower latency and it uses an IP-based infrastructure. LTE is the solution to mitigate the traffic load issue and it is being rolled out around the world. The proposed communication processor R-Mobile U2 (RMU2) achieves single-chip integration of a 1.5GHz dual-core application processor and a triple mode (GSM/WCDMA/LTE) base-band processor. Key design highlights of the RMU2 are: 1) A 28nm HKMG high-performance and low-leakage (HPL) CMOS bulk process achieves an optimal balance between both low leakage current and high performance. 2) A CPU clock control mechanism, called the “power saver”, limits the CPU power so as not to exceed a threshold level and to reduce IR drop. 3) The internal power domain is separated into 33 sub-blocks with I/O NMOS power switches [1] to minimize leakage current of any unused sub-block. 4) A dual-mode low-leakage SRAM [2] achieves low standby current in addition to conventional memory characteristics.

10.2 A 28nm HPM heterogeneous multi-core mobile application processor with 2GHz cores and low-power 1GHz cores

The worldwide demand for high-performance mobile or car infotainment application processors (AP) is increasing. This demand coexists with the need for low power to achieve long battery life and avoid thermal runaway. A heterogeneous CPU configuration is an effective solution. The proposed heterogeneous quad/octa-core AP has a combination of high-performance 2GHz cores and energy-efficient 1GHz cores. The maximum performance in the octa-core configuration is 35600 DMIPS. The key design highlights are: 1) Using a dedicated PLL and H-tree clock in the high-performance CPU achieves both 2GHz operation and reduced dynamic power. 2) A low-leakage SRAM in a 28nm HPM process is used and the leakage current of the peripheral circuits of the SRAM macro is optimized via multiple threshold voltages (Vt) and gate lengths (Lg). 3) The effects of process and voltage variations are accurately corrected by an on-chip process sensor and direct sensing of the voltage in the power mesh of the chip. 4) An enhanced CPU clock control mechanism is employed, which uses an on-chip delay sensor to reduce AC IR drop. 5) The heterogeneous CPU architecture maintains high performance even during thermal throttling.

Challenges of design and packaging for 3D stacking with logic and DRAM dies

A Wide IO DRAM controller chip with Through Silicon Via (TSV) technology is implemented. Test circuitry for prebonding TSV tests are embedded in between the fine pitch TSVs. In order to reduce Vmin degradation induced by 512 DQs simultaneously switching noise, we introduce a package-board impedance optimization method utilizing a full digital noise monitor. We also develop a 3D stacked flip chip assembly process with void less underfill enabled by Non Conductive Film (NCF). 12.8 GB/s operation is achieved, while IO power was reduced by 89% compared to LPDDR3.

Testability improvement for 12.8 GB/s Wide IO DRAM controller by small area pre-bonding TSV tests and a 1 GHz sampled fully digital noise monitor

We developed a Wide IO DRAM controller chip with Through Silicon Via (TSV) technology. Test circuitry is embedded in the micro-IOs placed between the fine pitch TSVs which can reject TSV connectivity failures prior to stacking process. In order to reduce Vmin degradation induced by 512 DQs simultaneously switching noise, we introduce a package-board impedance optimization method utilizing a full digital noise monitor. We achieved 12.8 GB/s operation, while IO power was reduced by 89 % compared to LPDDR3.

Power-Management Features of R-Mobile U2, an Integrated Application Processor and Baseband Processor

R-mobile U2 integrates an application processor and an LTE-capable triple-band baseband processor in 28-nm technology to provide rich content to the mid-range market. Several power-management techniques are equipped, including a low-leakage power switch, dual-standby mode static RAM (SRAM), and frequency control for maximum power suppression.

Design Challenges in 3-D SoC Stacked With a 12.8 GB/s TSV Wide I/O DRAM

Design techniques for 3-D SoC stacked with a Wide I/O DRAM with through silicon via (TSV) technology were developed. Some of the developed techniques were applied to design a Wide I/O DRAM controller chip. Micro-I/O cells and area efficient decoupling capacitor cells are implemented in between the fine pitch TSV array. Test circuitry for pre-bonding TSV tests are embedded in the micro-I/O cells with small area overhead. In order to reduce Vmin degradation induced by 512 DQs simultaneous switching noise, we introduce a package-board impedance optimization scheme utilizing a full digital noise monitor. We also developed a thermal aware memory control technique to adaptively change the refresh rates per channel, which are hot due to SoC hotspots. We achieved 12.8 GB/s operation, while I/O power was reduced by 89% compared to LPDDR3.

A 123μW standby power technique with EM-tolerant 1.8V I/O NMOS power switch in 28nm HKMG technology

We have developed a power-gating technique for a mobile processor in 28-nm HKMG technology. The proposed EM-tolerant 1.8V I/O NMOS power switch reduces the standby power to 1/641× and achieves 79% channel utilization without weakening EM immunity. The active leakage power of the dual CPU cores can be reduced by 45 mW in a single core operation mode with a rapid 1.4-μs wakeup time to full core operation. A mobile processor is designed and fabricated with proposed technique. Estimated standby power of the chip is 123 μW, resulting in one order of magnitude reduction compared to the conventional techniques. Measured leakage power shows a good agreement with the estimated one.