Ryo Tanaka

Fine Trench Patterns with Double Patterning and Trench shrink Technology

As part of the trend toward finer semiconductor design rules, studies have begun in the field of semiconductor lithography technology toward the 32nm-node and 22nm-node generations. The development of various types of fine-processing technologies is underway and particular progress is being made in the development of high numerical aperture (NA) technology and extreme ultraviolet (EUV) lithography for 32nm processes and beyond. At present, however, many technical issues are still being reported. One problem of special concern relates to the forming of fine, high-density trench patterns. Here, the required process margin is difficult to achieve by existing fine-processing techniques compared to lines and space patterns, and it is predicted that this problem could be a factor in lower yields caused by pattern defects. To solve this problem, studies have begun on double patterning technology and various shrink technologies. To place the joint use of these technologies on the road toward genuine mass-production applications, it is becoming increasingly important that comprehensive efforts be made to improving the basic performance of exposure-equipment and single lithography processes, to improving the alignment accuracy in double patterning, and to extract problem points in critical-dimension (CD) and defect control toward an exposure-equipment/ coater/developer cluster tool. In the face of these technical issues, NIKON Corporation and Tokyo Electron Ltd.(TEL) have joined forces to study technology for forming fine, high-density trench patterns and have successfully developed a fine, high-density trench-pattern formation process through the joint use of double patterning technology and original Chemical Vapor Deposition (CVD)-shrink technology. This paper reports on the results of a comprehensive process evaluation of double patterning technology using lithography clusters, CVD tools and etching tools.

Double patterning lithography study with high overlay accuracy

Double patterning (DP) has become the most likely candidate to extend immersion lithography to the 32 nm node and beyond. This paper focuses on experimental results of 32nm half pitch patterning using NSR-S620D, the latest Nikon ArF immersion scanner. A litho-freeze-litho (LFL) process was employed for this experiment. Experimental results of line CDU, space CDU, and overlay accuracy are presented. Finally, a budget for pitch splitting DP at the 22 nm half pitch is presented.

Immersion-cluster uptime enhancement technology toward high-volume manufacturing

In immersion lithography, importance is placed on technology for controlling coating along the edge of the wafer. In the case of a top-coat process, it has been observed that the top coat can peel off during immersion exposure due to weak adhesion to the substrate, a characteristic of top-coat films. The peeling of the film is thought to adversely affect immersion-exposure equipment and the wafer surface by the formation of defects due to the contamination of the immersion-exposure tool and by residual particles. Nikon Corporation and Tokyo Electron Ltd. (TEL) have performed joint research and development in response to these problems. TEL has studied rinsing technology for the wafer edge section and established coating processes and control techniques that rinse the edge section to remove foreign matter and that control the cutting position of each film in the edge section. TEL has developed new processes and hardware to remove foreign matter introduced into the immersion-exposure tool, and has shown that this technology can help prevent contamination of exposure equipment. Nikon has established efficient on-body periodic rinsing as a new technology for exposure equipment that can reduce defect.

TTR (through the reticle) alignment system with photoresist ablation technique

Various alignment methods for a semiconductor exposure tool have been proposed and developed. Especially, the TTR (through the reticle) alignment technique has been expected as the ideal system since the direct measure between a reticle and a wafer through the projection lens has no baseline error. However, it requires that an alignment illumination be a single wavelength of the exposure light because of the chromatic aberration of the projection lens. The strong absorption by the resist and the BARC (bottom anti reflective coating) weakens the alignment signal intensity, and the interference fringe in the resist by the single wavelength sacrifices the precise position detection. Such difficulty in signal detection has blocked the TTR system from becoming realized. We tried to address this problem by peeling the resist and BARC on alignment marks. To peel the resist and BARC, we performed elective ablation using a laser ablation method with the Q-switch Nd YAG laser. The laser-ablated alignment marks on some process wafers were measured by the TTR alignment system. The signal waves with enough contrast were measured over all wafers and the satisfied alignment accuracy was examined.