Vanessa Smet

Modeling, design, fabrication and characterization of first large 2.5D glass interposer as a superior alternative to silicon and organic interposers at 50 micron bump pitch

This paper describes the first design and fabrication of a large 2.5D glass interposer with 50 μm pitch chip-level interconnections made of 6 layers of 3 μm re-distribution (RDL) wiring. Many applications including high-performance networking and cloud computing data centers require ultra-high-bandwidth of the magnitude of 512 GB/s. Silicon-based 2.5D interposers are the only approaches being pursued by the industry to meet this need, enabled by sub-micron BEOL wiring in the wafer fabs. Such interposers, however, are too expensive for most applications. Glass interposers are superior to silicon interposers due to their high dimensional stability, low loss tangent, and large panel processing ultimately leading to lower cost. This paper presents the design, fabrication and electrical characterization, leading to the first fabrication of 2.5D glass interposers with 50 μm I/O pitch with 3 μm lines. Double-sided panel processing utilizing thin, low-loss dryfilm polymer dielectrics and SAP copper plating, with differential spray etching techniques, was used to fabricate 3 um wide transmission lines on 25mm × 30mm glass interposers processed on a 300 um thick 150mm × 150mm glass panels. A six-metal layer test vehicle with two daisy chain, 10mm × 10mm test chips at 100 μm spacing, was fabricated and assembled by thermo-compression bonding of Cu microbumps and SnAg solder caps. Ultra-fine 3 μm escape routing was demonstrated on a two-metal layer test vehicle. High frequency characterization of 3 μm lines showed low loss of 0.12 dB/mm at 2 GHz.

Low cost, high performance, and high reliability 2.5D silicon interposer

This paper presents the first demonstration of polycrystalline silicon interposers with fine pitch through package vias (TPV), with less than 5μm RDL lithography at 50μm pitch copper microbump assembly. Silicon interposers with through silicon vias (TSV) and back end of line (BEOL) wiring offer compelling benefits for 2.5D and 3D system integration; however, they are limited by high cost and high electrical loss. The polycrystalline Si interposer with 100-200μm thick raw Si, obtained without any back-grind or polish, and double side processing, without the use of carriers, has the potential to reduce the cost of wafer-based Si interposers by 2× and up to 10× by scaling to large panels. Thick polymer liner reduces the electrical loss of TPVs dramatically, by an order of magnitude compared to TSVs with SiO2 liner. Initial reliability of TPVs at 150μm and 200μm pitch was demonstrated with daisy chains passing 1000 thermal cycles from -55°C to 125°C. The paper concludes with Cu-SnAg microbump assembly at 50μm pitch onto panel Si interposers with Cu-polymer RDL routing at 4-5μm line lithography.

First demonstration of a surface mountable, ultra-thin glass BGA package for smart mobile logic devices

This paper presents the first demonstration of an ultra-thin glass BGA package that is assembled on to mother board with standard SMT technology. Such a package has many new advances that include ultra-thin glass, high speed through via hole formation and copper metallization, double-side RDL wiring with advanced 3 micron ground rules, and Cu-SnAg microbump assembly of a 10mm silicon test die. Glass, as a package, overcomes the shortcomings of organic packages in bump pitch, CTE mismatch to Si and warpage and silicon interposers in electrical performance and cost. Glass packages are being developed to manufacture both as wafers for improved performance over Si and as panels to improve bump pitch over organic packages. Glass, therefore, is not just a high performance and low volume technology, like silicon interposers, but a pervasive package technology with lower cost, higher performance and thinner than silicon and organic packages. Glass has compelling benefits in thickness and I/O pitch reduction and reliability for one of the highest volume applications, namely, the packaging of high I/O logic devices for smart mobile systems. This paper represents a paradigm shift in ultra-thin packages using large glass panels for future smart mobile and high performance devices, and the first demonstration of 100um thin glass packages with 50-80um c hip-level I/O pitch and 18 mm × 18mm body size surface mount assembly at 400um pitch.

Modeling, design and demonstration of low-temperature, low-pressure and high-throughput thermocompression bonding of copper interconnections without solders

High-throughput assembly technologies to form Copper (Cu) interconnections without solders at below 200°C, and pitch below 40μm has been a major challenge in the semiconductor industry. A unique solution has been demonstrated by Georgia Institute of Technology to overcome this grand challenge. This technology utilizes thermocompression bonding to form copper interconnections with process tolerances to accommodate non-coplanarities of bumps and warpage of the substrate, without solders. The bonding pressure applied for thermocompression was 365MPa, to enable Cu bump collapse by 3μm. As thermocompression bonders are generally force-limited to 400N, such high bonding pressures may hinder scalability of this technology to fine pitches with higher I/O densities. This paper addresses this manufacturability challenge with the novel Electroless Palladium Autocatalytic Gold (EPAG) surface finish instead of the standard Electroless Nickel Immersion Gold (ENIG) or Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG) finish, previously used to prevent Cu oxidation for bonding load reduction down to 120MPa.

First demonstration of drop-test reliability of ultra-thin glass BGA packages directly assembled on boards for smartphone applications

This paper reports the first demonstration of the drop-test reliability performance of large, ultra-thin glass BGA packages that are directly mounted onto the system board, unlike the current approach of flip-chip assembly of interposers, involving additional organic packages which are then SMT assembled onto boards. The packages, 18.4mm × 18.4mm in size made of 100μm-thick glass, were also successfully assembled, for the first time, in a SMT line. The effect on drop reliability of the glass BGAs with circumferential polymer collars was studied extensively. While the glass BGA packages met the reliability requirements, both with and without polymer collars, the polymer collars were found to further enhance the drop performance, as well as the fatigue life of solders. Finite element modeling was used to understand strain-relief mechanisms and provide design guidelines for reliability. The glass substrates fabrication process along with the formation of polymer collars by spin coating is detailed. The glass package-to-PCB assemblies were formed using SMT-compatible processes with standard equipment, followed by reliability testing through thermal cycling and drop tests. The compiled failure data from drop testing was fitted into a Weibull distribution plot. Comprehensive failure analysis was performed to assess the structural integrity of the glass substrates and identify the predominant failure mechanisms in drop test.

Large low-CTE glass package-to-PCB interconnections with solder strain-relief using polymer collars

This paper reports the use of circumferential polymer collars as a strain-relief mechanism to improve the fatigue life of low-CTE package-to-PCB solder interconnections, while preserving SMT-compatibility and reworkability. Acting as a partial underfill, the polymer-collar serves to block shear deformation at the solder-package interface, and redistributes the load to reduce the overall plastic strain concentration in the solders. It also suppresses failure initiation from defective surface sites and, thus further enhances reliability. Ultra-thin glass 100μm interposers were fabricated in 18.4 mm × 18.4 mm size to model, design and demonstrate the reliability enhancement with the polymer-collar approach. The detailed interposer design and fabrication process with laminated dielectric and metallization layers on both sides is presented. A new class of epoxies with low modulus, without the incorporation of silica fillers, was used to act as the polymer collars. The polymer collars are formed by spin-coating with an optimized thickness to provide the best compromise between the effective strain relief and reworkability. Board-level assembly was performed using standard SMT processes for glass interposers with and without polymer collars. Thermal cycling reliability testing (-40°C to 125°C) of interposers, assembled on PCBs with and without polymer collars for various thicknesses of the collar was performed.

A new era in manufacturable, low-temperature and ultra-fine pitch Cu interconnections and assembly without solders

This paper presents the first demonstration of a high-throughput die-to-panel assembly technology to form Cu interconnections without solder at temperatures below 200°C. This interconnection technology, previously established with individual single-chip packages on both organic and glass substrates, at pitches down to 30μm, is brought up to a significant manufacturable level by two major innovations: 1) ultra-fast thermocompression bonding (TCB) process with pre-applied polymer, in air, and without any prior surface activation; 2) die-to-panel assembly process with heating from die side exclusively for reduced substrate warpage. The initial proof of concept reported in this paper consists of assembly of 15 silicon dies with Cu bumps at 100 μm pitch, on a 3” × 5” organic substrate, by sequential TCB at 210°C for 3 seconds, and 190°C for 10 seconds. X-ray analysis, C-SAM imaging, cross-section observation with optical microscopy and SEM, and electrical yield characterization indicate the formation of strong metallurgical interconnections. This pioneering technology addresses many manufacturability challenges presently hindering the technology-transfer of direct Cu-Cu bonding, the “holy grail” in the semiconductor industry, by offering a potentially low-cost, high-throughput solution, compatible with industry-standard assembly lines. Scalable to ultra-fine pitches onto low-CTE glass, silicon or organic packages, it has the potential to become a major enabler for the next two or more decades.

Accelerated SLID bonding using thin multi-layer copper-solder stack for fine-pitch interconnections

Emerging 2.5D and 3D package-integration technologies for mobile and high-performance applications are primarily limited by advances in ultra-short and fine-pitch off-chip interconnections. A range of technologies are being pursued to advance interconnections, most notably with direct Cu-Cu interconnections or Cu pillars with solder caps. While manufacturability is still a major concern for the Cu-Cu interconnections technologies, the copper-solder approaches face limitations due to solder-bridging at fine-pitch, electromigration, and reliability issues. Thus, novel low-temperature, low-pressure, high-throughput, cost-effective and manufacturable technologies are needed to enable interconnections with pitches finer than 15 microns. This paper focuses on an innovative multi-layered copper-solder stack approach to achieve fine-pitch off-chip interconnections with no residual solders after assembly. Interconnections using this new technology enable higher current-handling because of the stable intermetallics, high-throughput assembly, and high yield even at low stand-off heights. The elimination of solder-intermetallic (IMC) interfaces is also expected to enhance the joint strength. This paper describes the design, fabrication, assembly and characterization of such stacked copper-solder interconnections. A detailed study of the effect of bonding parameters such as temperature and time on the rate of formation of stable Cu-IMC-Cu structures is presented. Test-vehicles were designed and fabricated as the first demonstration of this technology.

Interconnection materials, processes and tools for fine-pitch panel assembly of ultra-thin glass substrates

The needs for higher speed and bandwidth at low power for portable and high-performance applications has been driving recent innovations in packaging technologies with new substrate platforms with finer lithographic capability and dimensional stability, such as ultra-thin glass, to enable off-chip interconnections pitch scaling, down to 30μm. Copper pillar flip-chip thermocompression bonding (TCB) has subsequently become a pervasive technology in the past decade, and is now considered as the next interconnection and assembly node for smart mobile and high-performance systems. However, additional innovations are needed to achieve high-throughput thermocompression bonding on fragile and thin glass, with short cycle times and process conditions within HVM (high-volume manufacturing) tool capability. These include material advances in surface finishes and pre-applied underfill materials with built-in flux, along with a unique co-development strategy to provide high-speed solutions with optimized TCB profiles that consider the dynamic thermal behavior of high-density glass substrates, underfill curing kinetics, as well as tool compatibility. These innovations are the key focus of this paper. Finite element heat transfer and thermomechanical modeling were carried out to emulate assembly processes and compare the behavior of glass substrates to that of current technologies. Residual stresses created during the cool-down phase were extracted to help define process windows for stress management in interconnections, by fine control of intermetallics (IMC) formation. Emerging surface finish chemistries compatible with high-density wiring with sub-10μm spacings, such as OSP or EPAG (electroless Pd, autocatalytic Au) finish, were also evaluated for their effect on the formed IMC systems. A new set of no-flow snap-cure underfill materials with high thermal stability, beyond existing conductive films or pastes, was developed in synergy with tools and processes for compatibility with advanced substrate technologies. Model predictions were validated with assembly trials on ultra-thin glass and organic substrates with 100μm thin cores. Design guidelines for bonding tools, materials and processes were finally derived, for high-speed thermocompression bonding, customized to the performance, reliability and cost needs of next-generation mobile and high-performance systems.

Empirical investigations on die edge defects reductions in die singulation processes for glass-panel based interposers for advanced packaging

The authors evaluated various dicing methods in order to improve the TCT reliability against SeWaRe type of failures in glass interposers fabricated by polymer lamination over thin glass sheet cores. For blade-based dicing methods, the criteria for down-selection were (i) the least glass sidewall roughness and (ii) crack-free die edge visual inspections. In this fashion, a BKM dicing blade was identified that produced SeWaRe-free interposer dies upon dicing operations. Secondly, in order to compare the fracture strengths of glass produced by blade dicing with those of known methods, bare, thin glass sheet test specimens were made. In 2-point bending fracture strengths tests, glass strengths from three different blade dicing methods are similar to other score-and-break based separation methods. Lastly, a dicing process using a R&D laser system from DISCO Corp., which is not yet released-to-market, also successfully singulated the glass interposer samples. Samples produced by both blade and laser processes have been passing the TCT accelerated reliability tests.