Ryuta Okamoto

A 1/2.5 inch 5.2Mpixel, 96dB Dynamic Range CMOS Image Sensor with Fixed Pattern Noise Free, Double Exposure Time Read-Out Operation

A 1/2.5 inch, 5.2 Mpeixel CMOS image sensor with wide dynamic range operation mode is developed and its effectiveness for high contrast scene pictures is verified. The adopted algorithm for this operation is inherently free from fixed pattern noise generation which often resists the realization of mass production level wide dynamic range image sensors. The attained dynamic range is 96 dB with 12 bit output scheme.

A 1/2.5-inch 8Mpixel CMOS image sensor with a staggered shared-pixel architecture and an FD-boost operation

In order to shrink pixel sizes for mobile phone cameras, several shared-pixel architectures have previously been proposed [1–3]. However, the use of conventional shared-pixel architectures leads to a Gr/Gb sensitivity imbalance because the Gr pixel and the Gb pixel have a different layout structure when using a Bayer Color Filter Array (CFA) [3,4]. The Gr/Gb sensitivity imbalance causes conspicuous fixed-pattern noise in reproduced images [4]. In many cases, the noise level has a scene-color temperature dependence, due to the sensitivity imbalance caused by the attenuation of the incident light by the electromagnetic effect. Therefore, conventional shared-pixel architectures need complicated digital signal processing to properly correct for this Gr/Gb sensitivity imbalance.

A 187.5µVrms-read-noise 51mW 1.4Mpixel CMOS image sensor with PMOSCAP column CDS and 10b self-differential offset-cancelled pipeline SAR-ADC

Low-power and small-area implementations are essential in the mobile-phone market. Serial signal-processing architectures, in which signal-processing circuits such as a programmable-gain amplifier (PGA) and an ADC can be shared by column-level correlated double sampling (CDS) circuits, promise to reduce chip size and power consumption. However, conventional column CDS circuits composed of linear capacitors or NMOS capacitors (NMOSCAPs) with output buffers (OBUFs) still occupy a large footprint. In this work, to reduce the area and the power consumption of column CDS circuits while keeping high linearity, 1.5V PMOS capacitors (PMOSCAPs) are employed. These capacitors work as low-cost sample-and-hold (S/H) capacitors as well as voltage level-shifters by using body-terminal control. To reduce the power consumption of the ADC, instead of a conventional pipeline ADC, we propose a 10b self-differential offset-cancelled pipeline SAR-ADC. It operates with the reference voltage of the ADCs half full-scale voltage (Vfs), leading to a reduction of 80% switching power and 50% capacitor DAC (CDAC) area in the ADC. A black-level correction function is built in the ADC without any additional DACs. The proof-of-concept circuits are implemented in a 1.4Mpixel CMOS image sensor that consumes 51.0mW with a frame rate of 17fps and a read noise of 187.5μVrms at 8.1× analog gain.

6.7 A 1.2e− temporal noise 3D-stacked CMOS image sensor with comparator-based multiple-sampling PGA

This paper presents a 1.2e-, 3D-stacked CMOS image sensor (CIS) for mobile applications. A key motivation for using a stacked configuration is to minimize the chip area. Also, since numerous components must be integrated into the bottom chip, a scaled 65nm CMOS process is adopted for the bottom chip. The developed CIS features 1.2e- temporal noise with extremely high power efficiency by employing a multiple-sampling (MS) technique. A 2nd-order incremental ΔΣ ADC with inverter-based switched-capacitor integrator realizes the MS technique with low power [1]. However, an exponential number of samples are required to reduce the quantization noise, and conversion speed worsens with higher bit resolution. An extended counting ADC, which is a blend of folding integration and cyclic ADC, attains high resolution with reduced conversion time [2-3]. However, an op-amp with high open-loop gain is required for good linearity and column-to-column matching characteristics, which increases power consumption. Also it is not suitable for scaled CMOS technology. An alternative approach is a single-slope (SS) based MS technique [4], in which two SS-ADCs convert the same pixel signal, and the readout signal is averaged in the digital domain, but the noise improvement is limited to -3dB and the power consumption and area occupation are roughly doubled.