Nagataka Tanaka

Low-leakage-current and low-operating-voltage buried photodiode for a CMOS imager

A low-leakage current and low-operating-voltage buried-photodiode structure of CMOS image sensors has been developed. The new structure adopted a modified fabrication process as well as an additional shallow p+ layer structure that covers the entire surface of the deep n-type photodiode. The required operating voltage for complete charge transfer from the photodiode is 3.3 V. Furthermore, the leakage current level allows high-quality images comparable to those of CCD image sensors.

A White-RGB CFA-Patterned CMOS Image Sensor with Wide Dynamic Range

CMOS image sensors is important for mobile phone cameras. But, when very small pixel sizes are used, the sensor SNR is limited by photon shot noise. In order to improve the sensor SNR Honda and Luo proposed the use of a sensor with a white (W) pixel in the color filter area. The white pixel, however, saturates at low light levels and sufficient dynamic range cannot be obtained as a result. In order to overcome the dynamic range problem, we propose a CIS with a WRGB color filter array (two white pixels per 2x2 block) incorporating the wide dynamic-range (WDR) technology.

A 1/2.5 inch 5.2Mpixel, 96dB Dynamic Range CMOS Image Sensor with Fixed Pattern Noise Free, Double Exposure Time Read-Out Operation

A 1/2.5 inch, 5.2 Mpeixel CMOS image sensor with wide dynamic range operation mode is developed and its effectiveness for high contrast scene pictures is verified. The adopted algorithm for this operation is inherently free from fixed pattern noise generation which often resists the realization of mass production level wide dynamic range image sensors. The attained dynamic range is 96 dB with 12 bit output scheme.

A 2/3-in 2 million pixel STACK-CCD HDTV imager

A 2/3-in optical format 2 M pixel STACK-CCD imager has been developed. The STACK-CCD imager, overlaid with an amorphous silicon photoconversion layer, realizes a large signal charge handling capability of 1.0/spl times/10/sup 5/ electrons, a -140 dB smear noise and a 90 dB dynamic range with a newly introduced device configuration and its unique operation. The 5.0 /spl mu/m(H)/spl times/5.2 /spl mu/m(V) unit pixel imager with sufficiently low image lag has been realized by a novel bias charge injection scheme These device performances are the best ever achieved by a CCD HDTV imager. This is the first such imager satisfying the device performances required for a practical use 2/3-in 2 M pixel HDTV imager. >

A low driving voltage CCD with single layer electrode structure for area image sensor

A new single layer electrode two-phase CCD was studied for the purpose of realizing low driving voltage operation in inter-line transfer CCD (IT-CCD) image sensor aiming for low power consumption. Conventional H-CCD with overlapping double layer electrode structure have not achieved signal charge transfer at very low driving voltage below 2 V due to appearance of potential pocket under the inter-electrode gap yet. The new CCD employs a new channel doping profile for potential pocket suppression at the inter-electrode gap. The new CCD also employs a stepped-oxide structure having a single layer transfer electrode covering both a thin gate oxide forming storage region and a thinner gate oxide forming barrier region. The inter-electrode gap of single layer electrode was decreased to as small as 0.3 /spl mu/m. As a result of these measures, a fabricated 1/3 in format 270 K pixel IT-CCD image sensor reproduces a fine video image even when it is operated at a driving voltage as low as 1.8 V.

A 1/2.5-inch 8Mpixel CMOS image sensor with a staggered shared-pixel architecture and an FD-boost operation

In order to shrink pixel sizes for mobile phone cameras, several shared-pixel architectures have previously been proposed [1–3]. However, the use of conventional shared-pixel architectures leads to a Gr/Gb sensitivity imbalance because the Gr pixel and the Gb pixel have a different layout structure when using a Bayer Color Filter Array (CFA) [3,4]. The Gr/Gb sensitivity imbalance causes conspicuous fixed-pattern noise in reproduced images [4]. In many cases, the noise level has a scene-color temperature dependence, due to the sensitivity imbalance caused by the attenuation of the incident light by the electromagnetic effect. Therefore, conventional shared-pixel architectures need complicated digital signal processing to properly correct for this Gr/Gb sensitivity imbalance.

A single-layer metal-electrode CCD image sensor

A small pixel is required to reduce CCD image sensor chip size for commercial application. However, the shrinkage of pixel size adversely affects such characteristics as smear noise, sensitivity and charge-handling capability. Furthermore, a conventional overlapping double-layer polysilicon (polySi) electrode is complicated and difficult to fabricate for CCD image sensors. For process step simplicity of the transfer electrodes, aiming at low cost sensors and the smear noise reduction, a single-layer metal-electrode CCD image sensor is introduced.

Low Gr/Gb sensitivity imbalance 3.2M CMOS image sensor with 2.2μm pixel

For CMOS image sensors with pixel size under 3μm pixel, the pixel architecture in which several photodiodes share floating diffusion and transistors tends to be adopted in order to improve full well capacity and sensitivity. In spite even in the aforementioned advantage, adoption of the architecture may result in sensitivity imbalance between the shared photodiodes. On reproduced images obtained by the shared pixel architecture, sensitivity imbalance between Gr and Gb photodiodes in Bayer CFA is often conspicuous, because the imbalance results in horizontal pattern noise. We developed a low Gr/Gb sensitivity imbalance 3.2M CMOS Image Sensor with 2.2μm pixel. The pixel has the structure which is optically designed carefully in order to prevent light diffraction in pixel. According to a simulation result, read transistor gate for pixels with red color filter has an edgeless layout, because longer wave length light incident to the red pixels. For the optical design, electromagnetic analytical simulation was used because wave-optical effect cannot be ignored for the small pixel below 3μm. Gr/Gb sensitivity imbalance was measured for both the developed sensor and conventional sensor in visible light range. It was measured that the Gr/Gb sensitivity imbalance is below measurement limit.

Solid State Imaging Techniques. Study of Signal-Layer Metal-Electrode CCD Image Sensor.

A single-layer metal-electrode CCD image sensor was studied with the purpose of simplifying the steps in the production process with the aim of achieving low-cost sensors and supplressing smear noise. The inter-electrode gap of the single-layer electrode was decreased to 0.3 micrometer to achieve charge-transfer efficiency of unity. Boron ion-implantation which is self-aligned to the interelectrode gap was introduced to suppress degradation in charge-transfer efficiency. A reduction in the number of process steps needed to fabricate a 1/3-inch-format 360K-pixel interline transfer CCD image sensor was achieved. Vertical resolution was 350 TV lines. Low smear noise of-108dB was obtained.