Yoshitaka Egawa

A 2-million-pixel CCD image sensor overlaid with an amorphous silicon photoconversion layer

A highly sensitive 2-million-pixel high-definition charge-coupled device (CCD) image sensor was developed that features an overlaid amorphous silicon photoconversion layer on an interline transfer-type CCD scanner. The device is adapted to the 16:9 aspect ratio. 1125 scanning lines and 2:1 interlace high-definition TV system. A dual-channel horizontal CCD register is used to reduce the operating frequency to one half of the 74.25-MHz readout frequency. A horizontal period signal storage memory (1H line memory) is provided between the vertical CCD register and the horizontal CCD register to provide the signal distribution from the vertical CCD to the horizontal CCD register during the 3.77- mu s short horizontal blanking interval. This device realized a 1000 TV line horizontal limiting resolution 210 nA/1x high sensitivity. Total random noise was found to be 52 electrons RMS and a 72-dB dynamic range was achieved. >

A White-RGB CFA-Patterned CMOS Image Sensor with Wide Dynamic Range

CMOS image sensors is important for mobile phone cameras. But, when very small pixel sizes are used, the sensor SNR is limited by photon shot noise. In order to improve the sensor SNR Honda and Luo proposed the use of a sensor with a white (W) pixel in the color filter area. The white pixel, however, saturates at low light levels and sufficient dynamic range cannot be obtained as a result. In order to overcome the dynamic range problem, we propose a CIS with a WRGB color filter array (two white pixels per 2x2 block) incorporating the wide dynamic-range (WDR) technology.

A 1/2.5 inch 5.2Mpixel, 96dB Dynamic Range CMOS Image Sensor with Fixed Pattern Noise Free, Double Exposure Time Read-Out Operation

A 1/2.5 inch, 5.2 Mpeixel CMOS image sensor with wide dynamic range operation mode is developed and its effectiveness for high contrast scene pictures is verified. The adopted algorithm for this operation is inherently free from fixed pattern noise generation which often resists the realization of mass production level wide dynamic range image sensors. The attained dynamic range is 96 dB with 12 bit output scheme.

A Color CMOS Imager With 4

A color CMOS image sensor with the 4 times 4 White-RGB color filter array (CFA) including 50% white pixels has been developed. A transparent layer has been fabricated on the white pixel to realize over 95% transmission for visible light with wavelengths of 400-700 nm. Pixel pitch and number of the pixels were 3.3 mum and 2 million, respectively. With the simple and low-noise color separation process, low-illumination signal-to-noise ratios of luminance signal have been increased by 6 dB, compared with those of the Bayer pattern. Moreover, by locating the pixels so that every color components can be detected in every column and line, color artifacts at the edge were suppressed. The edge detection process became unnecessary and the process time was reduced by 70%. The new CFA has the potential to significantly increase the sensitivity of CMOS/CCD image sensors.

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Shrinking pixel size in conventional CCD imagers degrades device performance. Unsatisfactory smear noise of -90 dB is attained in a 2/3-inch 2M pixel CCD imager. The STACK-CCD imager has a great advantage regarding this problem. A 100% aperture ratio and low smear noise are maintained regardless of future pixel shrinking, because CCD scanning circuits are overlaid with an amorphous silicon (a-Si) photoconversion layer.<<ETX>>

4 White-RGB Color Filter Array for Increased Low-Illumination Signal-to-Noise Ratio

We have developed a CMOS image sensor with a novel color filter array(CFA) where one of the green pixels of the Bayer pattern was replaced with a white pixel. A transparent layer has been fabricated on the white pixel instead of a color filter to realize over 95% transmission for visible light with wavelengths of 400-700 nm. Pixel pitch of the device was 3.3 um and the number of pixels was 2 million (1600H x 1200V). The novel Bayer-like WRGB (White-Red-Green-Blue) CFA realized higher signal-to-noise ratios of interpolated R, G, and B values in low illumination (3lux) by 6dB, 1dB, and 6dB, respectively, compared with those of the Bayer pattern, with the low-noise pre-digital signal process. Furthermore, there was no degradation of either resolution or color representation for the interpolated image. This new CFA has a great potential to significantly increase the sensitivity of CMOS/CCD image sensors with digital signal processing technology.

A 2/3-inch 2M-pixel STACK-CCD imager

There are generally two approaches to dynamic range expansion for a solid-state imager. One is output-noise decrease. Another approach is a maximum signal-charge increase. An interline transfer CCD imager has an advantage in regard to low output noise, while its maximum amount of signal charges is lower than that for the other kinds of imagers, MOS, CPD, etc. Using a new operation mode, dynamic-range expansion for the interline transfer CCD imager has been achieved. There is a knee point in the photoelectric conversion characteristic.

A novel Bayer-like WRGB color filter array for CMOS image sensors

A 2/3-in optical format 2 M pixel STACK-CCD imager has been developed. The STACK-CCD imager, overlaid with an amorphous silicon photoconversion layer, realizes a large signal charge handling capability of 1.0/spl times/10/sup 5/ electrons, a -140 dB smear noise and a 90 dB dynamic range with a newly introduced device configuration and its unique operation. The 5.0 /spl mu/m(H)/spl times/5.2 /spl mu/m(V) unit pixel imager with sufficiently low image lag has been realized by a novel bias charge injection scheme These device performances are the best ever achieved by a CCD HDTV imager. This is the first such imager satisfying the device performances required for a practical use 2/3-in 2 M pixel HDTV imager. >

A photoelectric conversion-characteristic control method for interline transfer CCD imager

A high-light signal suppression operation, knee control operation, was evaluated in order to apply to a STACK-CCD of 2/3-in 2 M-pixel high definition television (HDTV) imager overlaid with an amorphous silicon photoconversion layer. A smooth bend was observed in the measured photoconversion characteristics near a knee point. It was analyzed theoretically by applying a subthreshold current of the MOSFET in weak inversion for skimming excess charges and reading out signal charges through a field shift gate. The calculated curve showed good agreement with the measured curve. Effectiveness of the knee control operation using the field shift gate was shown experimentally and theoretically over that using a conventional vertical overflow drain for IT-CCD imagers. >

A 2/3-in 2 million pixel STACK-CCD HDTV imager

Dual read-out register structure is indispensable for high definition television (IIDTV) CCD inage sensors to realize high signal read-out frequency (74.25MH2). llowever, this structure would suffer from a charge transfer loss between two read-out registers, unless precise care was taken in designing the registers. This paper describes the charge transfer loss nechanisn and proposes a new dual register structure, which can elininate this problen. As a result, the charge transfer loss is conpletely suppressed.