S.A. Hareland
University of Texas at Austin
Network
Latest external collaboration on country level. Dive into details by clicking on the dots.
Publication
Featured researches published by S.A. Hareland.
IEEE Transactions on Electron Devices | 1996
S.A. Hareland; S. Krishnamurthy; S. Jallepalli; Choh-Fei Yeap; K. Hasnat; A. Tasch; C.M. Maziar
Successful scaling of MOS device feature size requires thinner gate oxides and higher levels of channel doping in order to simultaneously satisfy the need for high drive currents and minimal short-channel effects. However, in deep submicron (/spl les/0.25 /spl mu/m gate length) technology, the combination of the extremely thin gate oxides (t/sub ox//spl les/10 nm) and high channel doping levels (/spl ges/10/sup 17/ cm/sup -3/) results in transverse electric fields at the Si/SiO/sub 2/ interface that are sufficiently large, even near threshold, to quantize electron motion perpendicular to the interface. This phenomenon is well known and begins to have an observable impact on room temperature deep submicron MOS device performance when compared to the traditional classical predictions which do not take into account these quantum mechanical effects. Thus, for accurate and efficient device simulations, these effects must be properly accounted for in todays widely used moment-based device simulators. This paper describes the development and implementation into PISCES of a new computationally efficient three-subband model that predicts both the quantum mechanical effects in electron inversion layers and the electron distribution within the inversion layer. In addition, a model recently proposed by van Dort et al. (1994) has been implemented in PISCES. By comparison with self-consistent calculations and previously published experimental data, these two different approaches for modeling the electron inversion layer quantization are shown to be adequate in order to both accurately and efficiently simulate many of the effects of quantization on the electrical characteristics of N-channel MOS transistors.
IEEE Transactions on Electron Devices | 1996
K. Hasnat; Choh-Fei Yeap; S. Jallepalli; W.-K. Shih; S.A. Hareland; V.M. Agostinelli; A. Tasch; C.M. Maziar
An energy parameterized pseudo-lucky electron model for simulation of gate current in submicron MOSFETs is presented in this paper. The model uses hydrodynamic equations to describe more correctly the carrier energy dependence of the gate injection phenomenon. The proposed model is based on the exponential form of the conventional lucky electron gate current model. Unlike the conventional lucky electron model, which is based on the local electric fields in the device, the proposed model accounts for nonlocal effects resulting from the large variations in the electric field in submicron MOSFETs. This is achieved by formulating the lucky electron model in terms of an effective-electric field that is obtained by using the computed average carrier energy in the device and the energy versus field relation obtained from uniform-field Monte Carlo simulations. Good agreement with gate currents over a wide range of bias conditions for three sets of devices is demonstrated.
IEEE Transactions on Electron Devices | 1997
K. Hasnat; Choh-Fei Yeap; S. Jallepalli; S.A. Hareland; W.-K. Shih; V.M. Agostinelli; A. Tasch; C.M. Maziar
A thermionic emission model based on a non-Maxwellian electron energy distribution function for the electron gate current in NMOSFETs is described. The model uses hydrodynamic equations to describe more correctly the electron transport and gate injection phenomena in submicron devices. A generalized analytical function is used to describe the high-energy tail of the electron energy distribution function. Coefficients of this generalized function are determined by comparing simulated gate currents with the experimental data. This model also includes the self-consistent calculation of the tunneling component of the gate current by using the WKB approximation, and by using a more accurate representation of the oxide barrier by including the image potential. Good agreement with gate currents over a wide range of bias conditions for three different technological sets of devices are demonstrated by using a single set of coefficients.
IEEE Transactions on Electron Devices | 1998
S.A. Hareland; M. Manassian; W.-K. Shih; S. Jallepalli; Haihong Wang; G. Chindalore; A. Tasch; C.M. Maziar
In this paper, models appropriate for device simulators are developed which account for the quantum mechanical nature of accumulated regions. Accumulation layer quantization is important in deep submicron (/spl les/0.25 /spl mu/m) MOS devices in the overlapped source/drain extension regions, in accumulation mode SOI devices, and in buried-channel PMOS structures. Computationally efficient models suitable for routine device simulation are presented that predict the reduction of the accumulated net electron (hole) sheet charge when quantization of the electron (hole) accumulation region is accounted for. The results of comparisons with self-consistent simulations support the validity of these models. In addition, simulation results will be shown which illustrate that when inversion layer quantum mechanical effects are modeled, it is also necessary to account for accumulation layer quantum mechanical effects in order to obtain more physically accurate as well as numerically stable solutions.
IEEE Transactions on Electron Devices | 1998
S.A. Hareland; S. Jallepalli; W.-K. Shih; Haihong Wang; G. Chindalore; A. Tasch; C.M. Maziar
As MOS devices have been successfully scaled to smaller feature sizes, thinner gate oxides and higher levels of channel doping have been used in order to simultaneously satisfy the need for high drive currents and minimal short-channel effects. With the onset and development of deep submicron (/spl les/0.25 /spl mu/m gate length) technology, the combination of the extremely thin gate oxides (t/sub ox//spl les/10 nm) and high channel doping levels (/spl ges/10/sup 17/ cm/sup -3/) results in transverse electric fields at the Si/SiO/sub 2/ interface that are sufficiently large, even near threshold, to quantize the motion of inversion layer carriers near the interface. The effects of quantization are well known and begin to impact the electrical characteristics of the deep submicron devices at room temperature when compared to the traditional classical predictions which do not take into account these quantum mechanical (QM) effects. For accurate device simulations, quantization effects must be properly accounted for in todays widely used moment-based device simulators. This paper describes a new computationally efficient three-subband model that predicts the effects of quantization on the terminal characteristics in addition to the spatial distribution of holes within the inversion layer. The predictions of this newly developed model agree very well with both the predictions of a self-consistent Schrodinger-Poisson solver and experimental measurements of QM effects in MOS devices.
IEEE Transactions on Electron Devices | 1997
S.A. Hareland; S. Jallepalli; G. Chindalore; W.-K. Shih; A. Tasch; C.M. Maziur
The effects of quantization of the inversion layer of MOSFET devices is an area of increasing importance as technology is aggressively scaled below 0.25 /spl mu/m. Although electron inversion layers have attracted considerable interest, very little work has been reported for holes. This paper describes the implementation and results of a simple, computationally efficient model, appropriate for device simulators, for predicting the effects of hole inversion layer quantization. This model compares very favorably with experimental results and the predictions of a full-band, self-consistent Schrodinger-Poisson solver.
IEEE Transactions on Electron Devices | 1998
G. Chindalore; J.B. McKeon; S. Mudanai; S.A. Hareland; W.-K. Shih; C. Wang; A. Tasch; C.M. Maziar
For the first time, experimental results are presented for electron and hole mobilities in the electron and hole accumulation layers of a MOSFET for a wide range of doping concentrations. Also presented is an improved methodology that has been developed in order to enable more accurate extraction of the accumulation layer mobility. The measured accumulation layer mobility for both electrons and holes is observed to follow a universal behavior at high transverse electric fields, similar to that observed for minority carriers in MOS inversion layers. At low to moderate transverse fields, the effective carrier mobility values are greater than the bulk mobility values for the highest doping levels. This is due to screening by accumulated carriers of the ionized impurity scattering by accumulated carriers, which dominates at higher doping concentrations. For lower doping levels, surface phonon scattering is dominant at low to moderate transverse fields so that the carrier mobility is below the bulk mobility value.
IEEE Transactions on Electron Devices | 2000
G. Chindalore; W.-K. Shih; S. Jallepalli; S.A. Hareland; A.F. Tasch; C.M. Maziar
This work presents for the first time experimental results for the extraction of the increase in the effective electrical oxide thickness (/spl Delta/t/sub ox/=t/sub ox,expt/-t/sub ox,physical/) in MOS accumulation layers with heavily doped substrates due to quantum mechanical (QM) effects, using experimentally measured MOS capacitance-voltage (C-V) characteristics and experimentally verified fullband self-consistent calculations. In addition, the fullband self-consistent simulations have been extended to accumulation regions, and the experimental results for the accumulation region have been compared with simulations. It has been shown that at moderate to high doping levels, /spl Delta/t/sub ox/ is as much as 0.4 to 0.5 nm for both electrons and holes, whereas for very high doping levels (>1/spl times/10/sup 19/ cm/sup -3/) /spl Delta/t/sub ox/ approaches zero. Thus, the experimental accumulation capacitance is predicted sufficiently well by the classical analysis itself.
international conference on microelectronic test structures | 1997
G. Chindalore; S.A. Hareland; S. Jallepalli; A.F. Fasch; C.M. Maziar; V.K.F. Chia; S. Smith
This paper reports the test structure and methodology that has been developed to experimentally extract the threshold voltage shifts due to quantum mechanical (QM) effects in both electron and hole MOS inversion layers. Compared to classical calculations, which ignore QM effects, these effects are found to cause a significant increase in the threshold voltage on the order of 100 mV in MOSFET devices fabricated with oxide thicknesses and doping levels anticipated for technologies with gate lengths /spl les/0.25 /spl mu/m. /spl Delta/V/sub T/ has been extracted from experimental devices with doping levels ranging from 5/spl times/10/sup 15/ cm/sup -3/ to 1/spl times/10/sup 18/ cm/sup -3/, and recently developed theoretical models are found to agree well with the results. Emphasis has been placed on developing a suitable test structure and methodology which enables the extraction of QM effects with little known error.
Vlsi Design | 1998
Haihong Wang; W.-K. Shih; Susan Green; S.A. Hareland; C.M. Maziar; A. Tasch
A quantum mechanical treatment of electron inversion layers is incorporated in the hydrodynamic (HD) transport model used in UT-MiniMOS. A physically based, yet computationally efficient, three-subband model is implemented in the HD simulation tool. The three-subband model, which is based upon solutions to Schrodingers equation, has the important advantage of more accurately predicting the distribution of electrons in the inversion layers than does more conventional classical models. A more simplified quantum mechanical model with carrier heating effects included has also been developed. Terminal currents are calculated using these quantum mechanical models and the comparison with results from classical calculations indicates the importance of quantum mechanical effects in the deep submicron device simulations.