P. Zeitzoff

The impact of high-/spl kappa/ gate dielectrics and metal gate electrodes on sub-100 nm MOSFETs

The potential impact of high-/spl kappa/ gate dielectrics on device short-channel performance is studied over a wide range of dielectric permittivities using a two-dimensional (2-D) simulator implemented with quantum mechanical models. It is found that the short-channel performance degradation is caused by the fringing fields from the gate to the source/drain regions. These fringing fields in the source/drain regions further induce electric fields from the source/drain to channel which weakens the gate control. The gate dielectric thickness-to-length aspect ratio is a proper parameter to quantify the percentage of the fringing field and thus the short channel performance degradation. In addition, the gate stack architecture plays an important role in the determination of the device short-channel performance degradation. Using double-layer gate stack structures and low-/spl kappa/ dielectric as spacer materials can well confine the electric fields within the channel thereby minimizing short-channel performance degradation. The introduction of a metal gate not only eliminates the poly gate depletion effect, but also improves short-channel performance. Several approaches have been proposed to adjust the proper threshold voltage when midgap materials or metal gates are used.

Dielectrics for future transistors

Abstract Responding to the market growth for computational power in various applications, semiconductor technology continues unabated in its drive towards higher transistor densities and faster transistors. The general direction of this trend is scaling down the critical transistor dimensions of integrated circuit (IC) components.

Interfacial Layer-Induced Mobility Degradation in High-

Analysis of electrical and scanning transmission electron microscopy (STEM) and electron energy loss spectra (EELS) data suggests that Hf-based high-k dielectrics deposited on a SiO2 layer modifies the oxygen content of the latter resulting in reduction of the oxide energy band gap and correspondingly increasing its k value. High-k deposition on thinner SiO2 films, below 1.1 nm, may lead to the formation of a highly oxygen deficient amorphous interfacial layer adjacent to the Si substrate. This layer was identified as an important factor contributing to mobility degradation in high-k transistors.

k

Response of the high-k gate dielectrics to low voltage stresses was studied by probing high-k transistors with various voltage/time measurements at different temperatures. The observed dependence of the transistor threshold voltage on stress time was attributed to electron trapping at pre-existing defects in the high-k dielectric rather than stress-induced trap generation. The dominance of the contribution from the reversible electron trapping on the pre-existing defects in the low voltage stress response raises the question on the applicability of the conventional reliability assessment methodology to the high-k dielectrics.

Transistors

The gate stack should be regarded as a multi-element interfacial layered structure wherein the high-k gate dielectric and gate electrodes (and their corresponding interfaces) must be successfully comprehended. The surface clean and subsequent surface conditioning prior to high-k deposition as well as post-deposition annealing parameters significantly impact the equivalent oxide thickness and leakage current as well as the traditional parameters such as threshold voltage, saturation current, transconductance, and sub-threshold swing. The control of both the fixed electrical charges and charge traps incorporated at the various interfaces and within the high-k bulk film is of paramount importance to achieve the requisite transistor characteristics and, in particular, the effective carrier mobility. Interactive effects within the gate stack process modules and the subsequent integrated circuit fabrication process require the utmost attention to achieve the desired IC performance characteristics and help facilitate the continuance of Moores Law towards the 10-nm physical gate length regime.

Effect of pre-existing defects on reliability assessment of high-K gate dielectrics

Fast transient charging effects (FTCE) are found to be the source of various undesirable characteristics of high-k devices, such as V/sub th/ instability, low DC mobility and poor reliability. The intrinsic characteristics of high-k transistors free from FTCE are demonstrated using ultra-short pulsed I-V measurements, and it is found that the intrinsic mobility of high-k devices can be much higher than what has been observed in DC based measurements. The FTCE model suggests that many of DC characterization methods developed for SiO/sub 2/ devices are not sufficiently adequate for high-k devices that exhibit significant transient charging. The existence of very strong concurrent transient charging during various reliability tests also degrades the validity of test results. Finally, the implication of FTCE on the high-k implementation strategy is discussed.

High-k gate stacks for planar, scaled CMOS integrated circuits

The speed performance of a double-gate (DG) FinFET CMOS with gate-source/drain (G-S/D) underlap is investigated using 2-D device and mixed-mode circuit simulation. By optimizing the G-S/D underlap, we demonstrate that the fin thickness of a DG FinFET can be significantly increased up to the physical gate length without degrading the speed performance compared to the conventional G-S/D overlap structure, where the fin thickness needs to be less than one-half of the physical gate length to control short-channel effects. Such an increase in fin thickness combined with a relaxed requirement for abruptness in the source/drain profile can dramatically enhance the manufacturability of DG FinFETs for the 32-nm technology node and beyond.

Intrinsic characteristics of high-k devices and implications of fast transient charging effects (FTCE)

A physically based correction for the impact of gate leakage current on the extraction of the effective mobility in MOSFETs has been derived that allows accurate determination of the mobility even when the gate leakage becomes significant. Experimentally, this correction has been applied to MOSFETs with both thin silicon dioxide and high-k gate dielectric, and the efficacy of the correction has been demonstrated for gate leakage up to 10 A/cm/sup 2/.

Highly Manufacturable Double-Gate FinFET With Gate-Source/Drain Underlap

A novel intrinsic mobility extraction methodology for high-/spl kappa/ gate stacks that only requires a capacitance-voltage and pulsed I/sub d/-V/sub g/ measurement is demonstrated on SiO/sub 2/ and high-/spl kappa/ gate dielectric transistors and is benchmarked to other reported mobility extraction techniques. Fast transient charging effects in high-/spl kappa/ gate stacks are shown to cause the mobility extracted using conventional dc-based techniques to be lower than the intrinsic mobility.

Correcting effective mobility measurements for the presence of significant gate leakage current

Fast electron trapping in high-k gate dielectrics is shown to effectively increase the magnitude of the threshold voltage during the dc measurements of the drain current, which leads to underestimation of the intrinsic channel carrier mobility. An approach based on the pulse Id-Vg technique is proposed to estimate a correction factor to the dc mobility.