S. C. Chien

The observation of trapping and detrapping effects in high-k gate dielectric MOSFETs by a new gate current Random Telegraph Noise (IG-RTN) approach

A new method, called gate current random telegraph noise (IG RTN), was developed to analyze the oxide quality and reliability of high-k gate dielectric MOSFETs. First, a single electron trapping/detrapping from process induced trap in nMOSFET was observed and the associated physical mechanism was proposed. Secondly, IG RTN has also been successfully applied to differentiate the difference in electron tunneling mechanism for a device under high-field or low-field stress. Finally, the soft-breakdown (SBD) behavior of a device can be clearly identified. Its IG RTN characteristic is different from that before soft-breakdown. It was found that SBD will indeed induce extra leakage current as a result of an additional breakdown path.

A Novel “hybrid” high-k/metal gate process for 28nm high performance CMOSFETs

A “hybrid” high-k/metal gate (HK/MG) integration scheme is proposed in this paper to accomplish HP (high performance) 28 nm CMOSFETs by integrating gate-first/gate-last (GF/GL) techniques for N/PFET, respectively. For NFET, remarkable mobility (95% of n⁺poly/SiON@1MV/cm) and low V<inf>TH</inf> (0.25 V) was achieved through optimized HfO<inf>2</inf> high-k, TiN metal and LaO<inf>x</inf> capping layer processes. For PFET, an extra 30% performance improvement and a low V<inf>TH</inf> (0.25V) were achieved by GL process as a result of strain boost and VFB roll-off alleviation [1].

More strain and less stress- the guideline for developing high-end strained CMOS technologies with acceptable reliability

In this paper, the design guideline with emphasis on CMOS device reliability has been addressed. Advanced 65 nm CMOS devices with various strain engineering were evaluated. For nMOSFETs, charge pumping (CP) measurement is efficient for their reliability characterizations. Although biaxial strained SiGe-channel device provides good driving current enhancement, it suffers from the Ge out-diffusion such that exhibits worse reliability. The SSOI device exhibits good hot-carrier immunity, but its interface quality needs special care during the process. In addition, SiC on S/D device is an alternative for high current enhancement, but its off-state junction leakage is serious. Then, CESL device becomes the most promising technology with high performance and the best reliability, especially with process simplicity. For pMOSFETs, both uniaxial and biaxial strained devices have been studied. For the first time, an accurate representation of interface trap (Nit) profiling, suitable for HC and NBTI analyses, has been developed by an improved DCIV method. The uniaxial-strained device shows much better reliability, in particular a special class of SiGe S/D device with EDB design seems to be promising. These results provide a valuable guideline for the aggressive design of strained CMOS technologies.

New Observations on the Uniaxial and Biaxial Strain-Induced Hot Carrier and NBTI Reliabilities for 65nm Node CMOS Devices and Beyond

In this paper, new observations on the uniaxial and biaxial strain-induced hot carrier reliability and/or NBTI in nMOSFET and pMOSFET respectively have been reported for the first time. Uniaxial and biaxial strained nMOSFET and pMOSFET have been extensively examined. Different mechanisms are responsible for different strains in nMOSFET and pMOSFET. For the nMOFETs, it was found that uniaxial strain device has comparable HC reliability with the control device, while biaxial SiGe-strained device exhibits a much worse reliability. This is related to a large impact ionization rate in a biaxial strain which leads to a much worse reliability. For the pMOSFETs, either uniaxial or biaxial strained device shows a comparable amount of HC degradation, while SiGe S/D strained structure might be better considering process complexity, performance, and reliability. Although NBTI is still a great concern in SiGe S/D devices, embedded SiGe S/D technique can improve greatly the device NBTI reliability. These results provide a valuable guideline for the present 65nm and beyond CMOS device design with focus on the strain engineering.

Mobility and Strain Effects on /(110) SiGe channel pMOSFETs for High Current Enhancement

Mobility and strain mechanisms of SiGe channel pMOSFETs fabricated with <110> channel direction on (110) Si substrate (<110>/(110) SiGe channel) have been studied in details for the first time. The combination of substrate orientation, high mobility channel material and extrinsic stained-Si process demonstrates the ultra high mobility enhancement and results in 80% current gain. The piezoresistance coefficients of <110>/(110) SiGe channel p-MOSFETs were also studied to analyze the strain effect on current enhancement. We also compared the derived piezoresistance coefficients results of SiGe channel on (100) and (110) surfaces

The Channel Backscattering Characteristics of Sub-100nm CMOS Devices with Different Channel/Substrate Orientations

The channel backscattering and injection velocity of carriers in advanced CMOS devices are the two key parameters for achieving high drain current enhancement. For the first time, an extensive study of these transport parameters for different substrate orientations has been evaluated for both nMOSFET and pMOSFET. By suitably choosing the substrate orientation, it may achieve a reduced backscattering and an increased injection velocity, which is preferable for designing high performance logic CMOS devices. Results show that, in pMOSFET, (110) substrate is preferred and current enhancement can be greatly enhanced in the <112> channel. In comparison, (110) substrate in nMOSFET has an adverse effect in reducing driving current as a result of poorer transport characteristics. Therefore, (100) substrate is expected for nMOSFET design. A guideline is then summarized for the optimum design of high performance CMOS devices.

Technology Roadmaps on the Ballistic Transport in Straln Engineered Nanoscale CMO0S Devices

As device channel length continues to scale beyond 90nm, carrier transport in the ballistic regime becomes critically important. In this paper, the strain engineering and its correlation to the ION current enhancement of CMOS devices in the ballistic regime has been examined. It was characterized by two parameters, the ballistic transport efficiency and the injection velocity. Experimental verifications on very high mobility n- and p-MOSFET channel/substrate orientations with various strains have been made. For nMOSFETs, it shows that uniaxial tensile-stress using CESL is more efficient in current enhancement than the biaxial stress with bulk strained-SiGe technique. For the pMOSFETs, compressive stress using uniaxial or biaxial has been evaluated for various structures. It was found that both ballistic efficiency and the injection velocity can be enhanced in a specific pMOS structure with appropriate combination of CESL and biaxial strain. The technology roadmaps have then been established from advanced 65 nm CMOS devices. These results provide a guideline for designing high performance strained technology for CMOS devices in the sub-100 nm regime.

A new insight into the degradation mechanisms of various mobility-enhanced CMOS devices with different substrate engineering

In this paper, the difference in degradation mechanism for different substrate engineered CMOS devices has been reported for the first time. These two different substrate engineering includes hybrid substrate engineering, with (100) and (110) orientations, and strained-Si devices. Different mechanisms are responsible for these two different mobility enhancement schemes. For strained-Si devices, it shows that the dominant mechanism for HC (hot carrier) and NBT (negative bias temperature) degradations is attributed to the lateral electric field resulting from the mobility enhancement. While for (110)/(100) substrate engineered devices, the dominant mechanism is due to the dangling bond of the surface. In other words, for (110)/(100) substrate, the device degradation is weakly dependent on the mobility enhancement while largely dependent on the bond strength. Finally, the difference in temperature dependence of HC and NBT has also been observed for both strained-Si and (110)/( 100) substrate devices. Sophisticated measurement techniques, charge pumping (CP) and gated-diode (GD) measurement, have been employed to understand these device mechanisms. These results provide a guideline for the device design and the understanding of related reliabilities in the popular strained-Si and hybrid substrate technology CMOS devices

New observation of an abnormal leakage current in advanced CMOS devices with short channel lengths down to 50nm and beyond

In this work, for the first time, an abnormal leakage current has been observed in MOSFET with 50 nm channel length and beyond. This effect shows that, in an ultra-short channel MOSFET, sub-threshold swing (SS) and Ioff are decreased for back-biased nMOSFET and pMOSFET. This effect is attributed to the BJT-induced current from the source to the drain. An experimental approach has been used to verify the existence of this BJT current component. As a consequence, this BJT current can be reduced with appropriate control of the SID-to-substrate junction. As an application of the approach to advanced embedded-SiC MOSFET with various splits, it was found that a higher band-offset of SID-to-substrate junction will give rise to a larger the BJT ballistic transport current. This provides us important information on reducing the leakage current for advanced CMOS with 50nm and beyond.