S. Chmielewski

Reduction in the Number of PAL Macrocells in the Circuit of a Moore FSM

Reduction in the Number of PAL Macrocells in the Circuit of a Moore FSM Optimization methods of logic circuits for Moore finite-state machines are proposed. These methods are based on the existence of pseudoequivalent states of a Moore finite-state machine, a wide fan-in of PAL macrocells and free resources of embedded memory blocks. The methods are oriented to hypothetical VLSI microcircuits based on the CPLD technology and containing PAL macrocells and embedded memory blocks. The conditions of effective application of each proposed method are shown. An algorithm to choose the best model of a finite-state machine for given conditions is proposed. Examples of proposed methods application are given. The effectiveness of the proposed methods is also investigated.

Modelling and synthesis of automata in HDLs

In the paper digital modelling and synthesis of automata in Hardware Description Languages is described. There is presented different kinds of automata and methods of realization using languages like VHDL and Verilog. Basic models for control units are: Finite State Machine (FSM), Algorithmic State Machine (ASM) and Linked State Machine (LSM). FSM, ASM and LSM can be represented graphically, which would help a designer to visualize and design in a more efficient way. On the other hand, a designer needs a fast and direct way to convert the considered designs into Hardware Description Language (HDL) codes for simulation and analysis it for synthesis and implementation.

Design of CPLD-based mealy FSMs with counters

A method is proposed for hardware reduction of CPLD-based Mealy FMSs logic circuit. The method is based on replacement of state register by state counter. The content of the counter can be increased during both conditional and unconditional transitions. There is an example of application of proposed method.

Design of FPGA-based Mealy FSMs with Counters

The article presents a novel method for diminishing the hardware amount in LUT-based Mealy FSMs. The method targets FSMs with state counters. It is based on replacement of FSM inputs by additional variables. To decrease the number of literals, the pairs of inputs are encoded. An example of synthesis is shown.

Optimization of FPGA-based Moore FSM

A metod is proposed for hardware reduction in FPGA-based Moore FSM. It is based on using two sources of codes. It reduces the number of LUTs in the FSM circuit. The results of investigations are shown.

Synthesis of Moore Finite State Machines based on pseudoequivalent states

Abstract A new two-stage method of FSMs synthesis for PAL-based CPLD is proposed. It is based on both the wide fan-in of PAL cells and existence of the classes of pseudoequivalent states of Moore FSM. The first step targets decreasing for the number of PAL cells used for implementing the input memory functions. The second step targets decreasing for the number of PAL cells in the block of microoperations. An example of application of the proposed method is given, as well as, results of experiments carried out for standard benchmarks.

Synthesis of control unit with refined state encoding for CPLD devices

The method of decrease in the number of PAL macrocells in logic circuit of Moore finite-state-machine (FSM) is proposed. Some peculiarities of Moore FSM such as existence of pseudoequivalent states and dependence of output functions on states as well as a wide fan-in of PAL macrocells are used to optimize the hardware amount (the number of PAL macrocells). It allows hardware amount decrease without decreasing in performance of the controlled digital system. The method is based on simultaneous application of optimal state assignment and transformation of the codes of pseudoequivalent states into codes of their classes. The proposed approach permits to decrease the hardware amount without decrease of digital system performance. An example of proposed method application is given, as well as the results of its investigation.

Hardware reduction for FSM - Based control units using PAL technology

The method of decrease in the number of PAL macrocells in logic circuit of Moore finite-state-machine (FSM) is proposed. Some peculiarities of Moore FSM such as existence of pseudoequivalent states and dependence of output functions on states as well as a wide fan-in of PAL macrocells are used to optimize the hardware amount (the number of PAL macrocells. It allows hardware amount decrease without decreasing in performance of the controlled digital system. The method is based on simultaneous application of optimal state assignment and transformation of the codes of pseudoequivalent states into codes of their classes. The proposed approach permits to decrease the hardware amount without decrease of digital system performance. An example of proposed method application is given, as well as the results of its investigation.

Reduction in the number of PAL macrocells for Moore FSM implemented with CPLD

A method of combined state assignment is proposed which targets on a decrease in the hardware amount (the number of PAL macrocells) in combinational part of Moore finite-state-machine (FSM). Some peculiarities of Moore FSM such as existence of pseudoequivalent states and dependence of output functions on states as well as a wide fan-in of PAL macrocells are used to optimize the hardware amount. It allows hardware amount decrease without decreasing in performance of the controlled digital system. The method is based on simultaneous application of refined state assignment and transformation of the codes of pseudoequivalent states into codes of their classes. The proposed approach permits to decrease the hardware amount without decrease of digital system performance. Example of proposed method application is given.