S. Chou

Investigation of DC Hot-Carrier Degradation at Elevated Temperatures for p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors of 0.13 µm Technology

In this study, n-channel metal–oxide–semiconductor field-effect transistors (nMOSFETs) having 20 and 32 A gate oxide thicknesses of 0.13 µm technology were used to investigate DC hot-carrier reliability at elevated temperatures up to 125 °C. The research also focused on the degradation of analog properties after hot-carrier injection. On the basis of the results of experiments, the hot-carrier degradation of Id,op (drain current defined on the basis of analog applications) is found to be the worst case among those of three types of drain current from room temperature to 125 °C. This result should provide valuable insight to analog circuit designers. As to the reverse temperature effect, the substrate current (Ib) commonly accepted as the parameter for monitoring the drain-avalanche-hot-carrier (DAHC) effect should be modified since the drain current (Id) degradation and Ib variations versus temperature have different trends. For the devices having a gate oxide thinner than 20 A, we suggest that the worst condition in considering hot-carrier reliability should be placed at elevated temperatures.

Temperature Effects on the Hot-Carrier Induced Degradation of pMOSFETs

Low voltages in various stress modes and temperatures were applied on two kinds of pMOSFETs to investigate the hot-carrier (HC) induced degradation. Contrary to conventional concepts, this investigation demonstrates that the worst conditions for pMOSFET HC reliability involves CHC mode and at high temperature. The severity of degradation of pMOSFETs has become comparable to their nMOSFET counterparts. A probable damage mechanism is suggested to involve the generation of interface states by the integration of HC and negative biased temperature effect (NBTI). A new empirical lifetime model is proposed in terms of applied voltages and temperatures

An investigation on substrate current and hot carrier degradation at elevated temperatures for nMOSFETs of 0.13 /spl mu/m technology

In this report, nMOSFETs having 20 Aring and 32 Aring gate oxide thickness of 0.13 mum technology are used to investigate DC hot carrier reliability at elevated temperatures up to 125degC. The research also focused on the degradation of analog properties after hot carrier injection. Based on the results of experiments, the hot carrier degradation of Id,op (defined based on analog application) is found to be the worst case from room temperature to 125degC. This result should be a valuable message for analog circuit designers. As to the reverse temperature effect, the substrate current (Ib) commonly accepted as the statues for monitoring the drain avalanche hot carrier (DAHC) effect should be modified since the drain current (Id) degradation and Ib variations versus temperature have different trends. For the devices having gate oxide thinner than 20 Aring, we suggest that the worst condition in considering hot carrier reliability should be placed at elevated temperature

Mismatches after Hot-Carrier Injection in Advanced Complementary Metal–Oxide–Semiconductor Technology Particularly for Analog Applications

In this paper, the impact of hot carrier stress on the mismatch properties of n and p metal–oxide–semiconductor (MOS) field-effect transistors (FETs) with different sizes produced using 0.15 µm complementary MOS (CMOS) technology is presented for the first time. The research reveals that hot-carrier injection (HCI) does degrade the matching properties of MOSFETs. The degree of degradation closely depends on the strength of the HC effect. Thus, it is found that, under the stress condition of drain avalanche hot carrier (DAHC), the properties of nMOSFETs rapidly and greatly become worse, but the changes are small for pMOSFETs. For analog circuit parameters, it is found that the after-stress lines of n and pMOSFETs exhibit a cross point in σ (ΔVt,op) drawings. It is suggested that the cross point can be used to indicate the minimal size in order for n and p pairs to have the same degree of ΔVt,op mismatch in designing analog circuits. In addition, interpretations for the differences between n and pMOSFETs and between ΔVt,op and Ids,op mismatches are provided with experimental verifications.

Power improvement for 65nm nMOSFET with high-tensile CESL and fast nonlinear behavior modeling

In this paper, the power gain improvements by stress contact etch stop layer (CESL) in a 65-nm nMOSFET were studied. Compared to the conventional nMOSFET, the device with CESL stress shows an extra 6% power gain enhancement for the increased stress in the channel region. This study also presents the polyharmonic distortion (PHD) model extraction by X-parameters measurement when the power transistor was designed to work far from 50 ohms. By mean of this model, the accurate nonlinear behaviors of nMOSFET were obtained rapidly.

On the reverse short-channel effect and threshold voltage roll-off controls for 90 nm node MOSFETs

Abstract In order to let device designers tune the short channel behavior of MOSFETs, a method is proposed in this work to demonstrate how to use LDD (lightly doped drain) and pocket implants to control RSCE (reverse short channel effect) and threshold voltage (Vt ) roll‐off. The method is based on the process parameters and silicon data of the 90 nm node technology of UMC (United Microelectronics Corporation). With the help of computers, 17 different process conditions of 8 different gate lengths were simulated using ISE TCAD to collect Vt variation data. Four characteristics representing the short channel behaviors of the MOSFETs were designed and extracted from the simulated data. Their empirical equations were also established subsequently. After verification, those mathematical models were demonstrated to help device designers in choosing the most suitable LDD and pocket implant parameters to generate required Vt characteristics.

Temperature dependence of substrate currents of MOSFETs under different drain and gate biases

In this study, the problem of substrate currents of metal-oxide-semiconductor field-effect transistors exhibiting different temperature dependence at different gate and drain voltages is investigated. The unsolved so-called ‘transition point’ problem is found to be ascribable to the different sensitivities of thermal kinetic energy and phonon scattering effects to the variation of drain voltages. To include the influence of temperature and gate voltage, a new mathematical model for substrate current is proposed, which also reveals that modeling using the lucky electron approach cannot obtain satisfactory accuracy and that the transverse electrical field from gate bias is not a negligible factor. With the evidence from experiments, this article also points out that using the substrate current to monitor the severity of the hot-carrier effect is not reliable when the drain voltage is lower than the transition point.

New Insights into Flicker Noise Improvement Mechanism Using Random Telegraph Signal Technique

Abstract The conventional flicker (1/f) noise improvement approaches such as fluorine incorporation and hydrogen sintering are interpreted, for the first time, by detecting the border traps using the random telegraph signal (RTS) technique. The results show that the improvement in low frequency noise by F-incorporation can be mainly attributed to the relaxed trap-to-carrier influence. On contrary, the H2-annealing is found to improve the low frequency noise by the reduced trap density. Introduction The 1/f noise in MOSFETs has been studied for several decades due to its significant influence on the high frequency performance of the analog circuits [1]. The 1/f noise has also been regarded as one of the important techniques for the border traps characterization [2, 3]. Border traps will be increasingly important in the ultra-thin gate oxide where all the oxide traps may act as border traps on the conventional time scale of the noise measurement (Fig. 1). F-incorporation is known as an effective way to improve the conventional SiO2 gate dielectric integrity, and both the reliability and 1/f noise [4] improvement have been reported. Moreover, H2-sintering is found to influence the electrical performance of MOS devices and improve the interface quality [5]. In this work, we report a detailed characterization of border traps in F-incorporated and H2-annealed SiON gate dielectric using the drain current-RTS (Id-RTS) technique [6] to investigate the mechanisms responsible for the 1/f noise improvement. Device Fabrication The 65nm technology was used for devices fabrication. Three categories of devices were prepared. The first one is F-incorporated device fabricated by receiving additional F-implant step. The second one is H2-annealed device fabricated by subjecting to additional low temperature H2 sintering step. And the third one is the control device. In an attempt to be helpful for RTS measurement, devices with small channel area were prepared. All devices have SiON gate dielectric with EOT=2.6nm. Results and Discussion Several kinds of applications had been reported for RTS technique in the past decades. Table-I summarizes the equations [1] for traps characterization, and the definitions of parameters can be found in Fig. 2-3. Firstly, Fig. 4 shows the measured Id-RTS of nFET with small area (L=0.06um, W=1um) under constant Vd and varying Vg. According to the trend of ton versus Vg, one can determine the type of detected border trap as acceptor-like trap or donor-like trap. Simultaneously, the correlation between ton and toff to mean capture tc and mean emission time te can be decided as well. For instance, a decreasing ton with the increasing Vg in Fig. 5 exhibits that the detected border trap is an acceptor-like trap, and the mean capture (emission) time tc (te) can be correlated to ton (toff). Secondly, in the plot of ln(tc/te) versus Vg (Fig. 6), the fitted slope can be used to extract the depth of the detected border trap from the dielectric/substrate interface (xT). Thirdly, the location of detected trap along the channel (yT) can be determined by Id-RTS along with changing the polarity of source and drain. The different surface potential under forwardand reverse-mode operation can be utilized to determine the trap location in the longitudinal direction (Fig. 7). Fourthly, the Id-RTS measurement under varying temperature allows one to extract the capture (emission) activation energy, Ec (Ee), of the detected trap (Fig. 8). Finally, the Id-RTS amplitude has also been reported to reveal the valuable information [7]. The screened scattering coefficient (α) is a key parameter in the reported unified 1/f noise model [8] and can be extracted from the Id-RTS amplitude using equation (4) in Table-I. Two mechanisms may be solely or jointly responsible for the 1/f noise improvement. The one is the reduced trap density, and the other is the relaxed trap-to-carrier influence. Fig. 9 shows an obvious improvement in low frequency noise is achieved by F incorporation. To distinguish the mechanism, Fig. 10 compares the mapping results where the location of die with digitized Id-RTS is highlighted. No obviously difference in the die number implies that the F incorporation does not help to reduce the border trap density. Instead, the noticeable lower (~0.5X) average Id-RTS amplitude (<∆Id>) in F-incorporated device reveals that the 1/f noise improvement can be attributed to the relaxed trap-to-carrier influence which is usually interpreted in terms of number fluctuation and/or mobility fluctuation [9, 10]. Fig. 11 shows the 1/f noise performance of control and H2-annealed devices. Similarly, the border trap density and the trap-to-carrier influence are evaluated. In Fig. 12, for H2-annealed wafer, a remarkable increase (~2X) in the number of die with digitized RTS reveals that the border trap density is effectively reduced. The lower trap density enhances the probability of probing a single trap for a given device channel area. It is suspected that the Hydrogen passivation can neutralize not only the interface traps but also the border traps. It is worth to note that the average Id-RTS amplitudes between control and H2-annleled devices are comparable. Differing from the case with F incorporation, the H2 sintering has no obvious effect on relaxing the trap-to-carrier influence as can be observed from the distribution of ∆Id shown in Fig. 13. Conclusion For the first time, the detection of border traps using RTS technique is applied to interpret the mechanisms responsible for the low-frequency-noise improvement. The relaxed trap-to-carrier influence can be observed in devices with F incorporation. On contrary, the reduced trap density is found in devices with H2 sintering.

Effects of Negative Bias Temperature Stress-induced Degradation and Mismatch on pMOSFETs in 90 nm Technology

It is well-known that the important reliability issues include drain avalanche hot-carrier (DAHC), channel hot-carrier (CHC), and negative bias temperature instability (NBTI). Early researches reported that pMOSFETs showed the worst degradation at DAHC and room temperature if cryogenic operation is unnecessary [1-2], but, based on 0.13 µm technology, our recent study showed that the worst case of HC has switched from DAHC to CHC and from low to high temperature. And the mechanisms pMOSFETs’ degradation are related to bias temperature instability (BTI) effect plus reverse temperature effect [3-4]. Presently, NBTI-induced pMOSFET deg-radation is becoming more serious as feature dimension is continu-ously shrinking [5-7]. NBTI becomes the popular reliability issue in future CMOS applications. Also, the matching of electrical properties between the identical transistor pairs on the same dice is important for wafer manufactur-ers and circuit designers. The foregoing reliability issues are the critical factor to induce transistor mismatches. An early study indi-cated that the mismatches of nMOSFETs’ current gain factors (β, β

Strained and Unstrained InGaAs/InP Quantum-Well Infrared Infrared Photodetectors Prepared by Metal Organic Chemical Vapor Deposition

1 Institute of Microelectronics & Department of Electrical Engineering, National Cheng Kung University, Taiwan No.1, University Road, Tainan City 701, Taiwan LandMark Optoelectronics Corporation, Tainan 700, Taiwan Research Center for Applied Sciences, Academia Sinica, Taiwan 128 Sec. 2, Academia Rd., Nankang, Taipei 11529, Taiwan Phone: +886-3-574-4364 E-mail: shihyen@gate.sinica.edu.tw Deaprtment of Photonics, National Chiao-Tung University, Taiwan 1001 University Road, Hsinchu 300, Taiwan