Joe Ko

Anomalous reverse short-channel effect in p/sup +/ polysilicon gated P-channel MOSFET

The boron-penetration-dependent Reverse Short Channel Effect (RSCE) on the threshold voltage is observed for short channel p/sup +/ poly-gate PMOSFETs. The RSCE is found to be more significant as the boron penetration becomes more severe. The RSCE is significant in BF/sub 2/ doped poly-gated MOS devices and is alleviated in buffered poly-gated MOS devices. Fluorine enhanced boron diffusion in the gate oxide during high temperature process is believed to account for the RSCE, which is also confirmed by using a two-dimensional process simulator.<<ETX>>

Investigation of DC Hot-Carrier Degradation at Elevated Temperatures for p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors of 0.13 µm Technology

In this study, n-channel metal–oxide–semiconductor field-effect transistors (nMOSFETs) having 20 and 32 A gate oxide thicknesses of 0.13 µm technology were used to investigate DC hot-carrier reliability at elevated temperatures up to 125 °C. The research also focused on the degradation of analog properties after hot-carrier injection. On the basis of the results of experiments, the hot-carrier degradation of Id,op (drain current defined on the basis of analog applications) is found to be the worst case among those of three types of drain current from room temperature to 125 °C. This result should provide valuable insight to analog circuit designers. As to the reverse temperature effect, the substrate current (Ib) commonly accepted as the parameter for monitoring the drain-avalanche-hot-carrier (DAHC) effect should be modified since the drain current (Id) degradation and Ib variations versus temperature have different trends. For the devices having a gate oxide thinner than 20 A, we suggest that the worst condition in considering hot-carrier reliability should be placed at elevated temperatures.

Temperature Effects on the Hot-Carrier Induced Degradation of pMOSFETs

Low voltages in various stress modes and temperatures were applied on two kinds of pMOSFETs to investigate the hot-carrier (HC) induced degradation. Contrary to conventional concepts, this investigation demonstrates that the worst conditions for pMOSFET HC reliability involves CHC mode and at high temperature. The severity of degradation of pMOSFETs has become comparable to their nMOSFET counterparts. A probable damage mechanism is suggested to involve the generation of interface states by the integration of HC and negative biased temperature effect (NBTI). A new empirical lifetime model is proposed in terms of applied voltages and temperatures

An investigation on substrate current and hot carrier degradation at elevated temperatures for nMOSFETs of 0.13 /spl mu/m technology

In this report, nMOSFETs having 20 Aring and 32 Aring gate oxide thickness of 0.13 mum technology are used to investigate DC hot carrier reliability at elevated temperatures up to 125degC. The research also focused on the degradation of analog properties after hot carrier injection. Based on the results of experiments, the hot carrier degradation of Id,op (defined based on analog application) is found to be the worst case from room temperature to 125degC. This result should be a valuable message for analog circuit designers. As to the reverse temperature effect, the substrate current (Ib) commonly accepted as the statues for monitoring the drain avalanche hot carrier (DAHC) effect should be modified since the drain current (Id) degradation and Ib variations versus temperature have different trends. For the devices having gate oxide thinner than 20 Aring, we suggest that the worst condition in considering hot carrier reliability should be placed at elevated temperature

Mismatches after Hot-Carrier Injection in Advanced Complementary Metal–Oxide–Semiconductor Technology Particularly for Analog Applications

In this paper, the impact of hot carrier stress on the mismatch properties of n and p metal–oxide–semiconductor (MOS) field-effect transistors (FETs) with different sizes produced using 0.15 µm complementary MOS (CMOS) technology is presented for the first time. The research reveals that hot-carrier injection (HCI) does degrade the matching properties of MOSFETs. The degree of degradation closely depends on the strength of the HC effect. Thus, it is found that, under the stress condition of drain avalanche hot carrier (DAHC), the properties of nMOSFETs rapidly and greatly become worse, but the changes are small for pMOSFETs. For analog circuit parameters, it is found that the after-stress lines of n and pMOSFETs exhibit a cross point in σ (ΔVt,op) drawings. It is suggested that the cross point can be used to indicate the minimal size in order for n and p pairs to have the same degree of ΔVt,op mismatch in designing analog circuits. In addition, interpretations for the differences between n and pMOSFETs and between ΔVt,op and Ids,op mismatches are provided with experimental verifications.

Charge Loss Due to AC Program Disturbance Stresses in EPROMs

Charge loss in interpolyoxide erasable programmable read-only memories (EPROMs) due to program disturbance by alternating current pulses applied to the drain was studied for the first time. It was found that the charge loss due to ac stress is more severe than that due to dc stress. Experimental results reveal that the more positive the floating gate potential, the more severe is the drain ac disturbance observed. The main reason for the charge loss is the displacement current which agitates the charges in the floating gate, creating a leakage path from the floating gate to the drain, in which the drain-to-floating-gate overlapping capacitance Cfd plays an important role. The drain dc stresses of interpolyoxide/nitride/oxide (ONO) EPROMs were also measured under different bias conditions and temperatures. The data show that higher dc electric field of the floating gate to the drain results in larger Vth shift, which can be accelerated by elevated temperature. In addition, the control gate ac stress-enhanced drain dc disturbance was also measured. We proposed that the dc drain stress is applied during the ac gate stress, which results in a heating effect. The results support the concept of dielectric ac heating.

Effect of etch stop layer stress on negative bias temperature instability of deep submicron p-type metal-oxide-semiconductor field effect transistors with dual gate oxide

Negative bias temperature instability (NBTI) in a dual-gate-oxide complementary metal–oxide–semiconductor (CMOS) process induces threshold voltage (Vt) shift and has become a crucial challenge in designing advanced analog or mixed-signal circuits. In this paper, the impact of the stress from a contact etch stop layer (CESL) on the NBTI of dual-gate-oxide input/output (I/O) p-type MOS field effect transistors (P-MOSFETs) is investigated in detail. Experimental results show that applying tensile stress can suppress NBTI-induced Vt shift more significantly than applying compressive stress, thus becoming a simple and effective method of relieving NBTI.

On the reverse short-channel effect and threshold voltage roll-off controls for 90 nm node MOSFETs

Abstract In order to let device designers tune the short channel behavior of MOSFETs, a method is proposed in this work to demonstrate how to use LDD (lightly doped drain) and pocket implants to control RSCE (reverse short channel effect) and threshold voltage (Vt ) roll‐off. The method is based on the process parameters and silicon data of the 90 nm node technology of UMC (United Microelectronics Corporation). With the help of computers, 17 different process conditions of 8 different gate lengths were simulated using ISE TCAD to collect Vt variation data. Four characteristics representing the short channel behaviors of the MOSFETs were designed and extracted from the simulated data. Their empirical equations were also established subsequently. After verification, those mathematical models were demonstrated to help device designers in choosing the most suitable LDD and pocket implant parameters to generate required Vt characteristics.

A New Drain Engineering Structure-SCD-LDD (Surface Counter Doped LDD) for Improved Hot Carrier Reliability

A new SCD-LDD (Surface Counter Doped LDD) structure is proposed. This structure introduces an additional oblique BF2 implant after nLDD implant, which counter-dopes the nLDD surface concentration near the gate edge. As a result, the lateral electric fields beneath the gate were reduced and the saturation drain current was conducted downward away from the maximum electric fields, resulting in a substantial enhancement of hot carrier reliability due to suppression of hot carrier generation and injection with this structure.

Temperature dependence of substrate currents of MOSFETs under different drain and gate biases

In this study, the problem of substrate currents of metal-oxide-semiconductor field-effect transistors exhibiting different temperature dependence at different gate and drain voltages is investigated. The unsolved so-called ‘transition point’ problem is found to be ascribable to the different sensitivities of thermal kinetic energy and phonon scattering effects to the variation of drain voltages. To include the influence of temperature and gate voltage, a new mathematical model for substrate current is proposed, which also reveals that modeling using the lucky electron approach cannot obtain satisfactory accuracy and that the transverse electrical field from gate bias is not a negligible factor. With the evidence from experiments, this article also points out that using the substrate current to monitor the severity of the hot-carrier effect is not reliable when the drain voltage is lower than the transition point.