Shuang-Yuan Chen

Interfacial and Electrical Characterization in Metal?Oxide?Semiconductor Field-Effect Transistors with CeO2 Gate Dielectric

Metal–oxide–semiconductor capacitors (MOSCs) and MOS field-effect transistors (MOSFETs) incorporating cerium dioxide (CeO2) dielectrics were fabricated and investigated. In this work, the electrical and interfacial properties were characterized by capacitance–voltage (C–V) and current–voltage (I–V) measurements. The density of interface trap per unit area (Nit), the density of interface trap per unit area and energy (Dit), the energy distribution of interface trap density, and the effective capture cross section (σs) were studied in details. Experimental results showed that the Nit, Dit, and σs were about 3.4×1010 cm-2, 7.3×1010 cm-2 eV-1, and 9.0×10-15 cm2, respectively. In addition, a comparison of interfacial properties among several gate dielectrics was made.

Interface trap generation and recovery mechanisms during and after positive bias stress in metal-oxide-semiconductor structures

Interface trap (Nit) generation and their partial recovery during and after cessation of the positive bias-temperature stress (PBTS) in n-type metal-oxide-semiconductor capacitors have been investigated. The analysis of experimental results indicates that Nit creation is caused by the depassivation of Si3≡Si-H bonds at the Si/SiO2 interface by the atomic neutral hydrogen (H0) cracked via electron impact at or near gate/oxide interface during electron injection from the substrate. Nit recovery after interruption of the stress is due to back diffusion of H2 species toward the Si/SiO2 interface and repassivation of Si3≡Si• dangling bonds. We propose that in absence of holes, a modified one dimensional reaction-diffusion (R-D) model following three step degradation sequences can qualitatively explain the generation and the recovery of Nit during and after PBTS.

Investigation of DC Hot-Carrier Degradation at Elevated Temperatures for p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors of 0.13 µm Technology

In this study, n-channel metal–oxide–semiconductor field-effect transistors (nMOSFETs) having 20 and 32 A gate oxide thicknesses of 0.13 µm technology were used to investigate DC hot-carrier reliability at elevated temperatures up to 125 °C. The research also focused on the degradation of analog properties after hot-carrier injection. On the basis of the results of experiments, the hot-carrier degradation of Id,op (drain current defined on the basis of analog applications) is found to be the worst case among those of three types of drain current from room temperature to 125 °C. This result should provide valuable insight to analog circuit designers. As to the reverse temperature effect, the substrate current (Ib) commonly accepted as the parameter for monitoring the drain-avalanche-hot-carrier (DAHC) effect should be modified since the drain current (Id) degradation and Ib variations versus temperature have different trends. For the devices having a gate oxide thinner than 20 A, we suggest that the worst condition in considering hot-carrier reliability should be placed at elevated temperatures.

Electron detrapping in thin hafnium silicate and nitrided hafnium silicate gate dielectric stacks

The kinetics of zero-field and field-induced detrapping of electrons trapped in HfSixOy and HfSiON after positive bias stress on n+-polycrystalline silicon (polySi) gate of n-type metal-oxide-semiconductor (nMOS) capacitors are experimentally investigated. The self detrapping follows a simple logarithmic relation with time while field-induced detrapping upon reversing the stress voltage obeys a simple first-order exponential decay suggesting mono energetic shallow traps associated with tunnel emission of trapped electrons. Finally, our investigation raises questions about the validity of the widely used distributed capture cross section model of electron traps to explain the threshold voltage instability in MOS devices with hafnium silicate gate stacks.

The influence of Hf-composition on atomic layer deposition HfSiON gated metal-oxide-semiconductor field-effect transistors after channel-hot-carrier stress

Metal–oxide–semiconductor field-effect transistors (MOSFETs) incorporating hafnium-silicate (HfSiON) dielectrics with different compositions have been fabricated and their hot-carrier injection (HCI) reliability has also been investigated. The experimental results reveal that the HCI degradation of atomic layer deposition (ALD) HfSiON gate dielectrics is minimized at Hf : Si = 1 : 3. Moreover, the experimental results also show that the increment of oxide trapped charges (ΔNot) depends on Hf content and is about one order of magnitude larger than that of interface traps (ΔNit) after channel-hot-carrier (CHC) stress. Finally, some important interfacial parameters, including ΔNit, ΔDit, and ΔNot, have also been characterized through the charge pumping (CP) technique.

Temperature Effects on the Hot-Carrier Induced Degradation of pMOSFETs

Low voltages in various stress modes and temperatures were applied on two kinds of pMOSFETs to investigate the hot-carrier (HC) induced degradation. Contrary to conventional concepts, this investigation demonstrates that the worst conditions for pMOSFET HC reliability involves CHC mode and at high temperature. The severity of degradation of pMOSFETs has become comparable to their nMOSFET counterparts. A probable damage mechanism is suggested to involve the generation of interface states by the integration of HC and negative biased temperature effect (NBTI). A new empirical lifetime model is proposed in terms of applied voltages and temperatures

An investigation on substrate current and hot carrier degradation at elevated temperatures for nMOSFETs of 0.13 /spl mu/m technology

In this report, nMOSFETs having 20 Aring and 32 Aring gate oxide thickness of 0.13 mum technology are used to investigate DC hot carrier reliability at elevated temperatures up to 125degC. The research also focused on the degradation of analog properties after hot carrier injection. Based on the results of experiments, the hot carrier degradation of Id,op (defined based on analog application) is found to be the worst case from room temperature to 125degC. This result should be a valuable message for analog circuit designers. As to the reverse temperature effect, the substrate current (Ib) commonly accepted as the statues for monitoring the drain avalanche hot carrier (DAHC) effect should be modified since the drain current (Id) degradation and Ib variations versus temperature have different trends. For the devices having gate oxide thinner than 20 Aring, we suggest that the worst condition in considering hot carrier reliability should be placed at elevated temperature

Heat stress exposing performance of deep-nano HK/MG nMOSFETs using DPN or PDA treatment

Abstract Decoupled plasma nitridation (DPN) or post-deposition annealing (PDA) process after high-k (HK) deposition to repair the bulk traps or the oxygen vacancy in gate dielectric is an impressive choice to raise up the device performance. Before heat stress, the electrical performance in drive current, channel mobility and subthreshold swing with both treatments was approximate, except the higher annealing atmosphere causing the thicker interfacial layer and reducing the overall related dielectric constant. After temperature stress, the electrical performance for all of the tested devices was slightly deteriorated. The degradation degree for electrical performance with PDA treatment group was the worst case due to NH3 atmosphere forming Si–H bond on the channel surface, which was broken after stress and produced more interface state reflected with the increase of subthreshold swing.

Electrical performance of a-Si:H and poly-Si TFTs with heating stress

The amorphous channel (a-Si:H) TFT-LCD technology dominates the large-area flat panel display (FPD) market, but a-Si:H TFTs propose some adverse characteristics, especially in mobility. Therefore, developing poly-Si TFTs to promote mobility and implement the chip-on-glass (CoG) dream is indeed necessary. Using a green continuous-wave laser on amorphous silicon channel formed as poly-crystallization is a possible way in increasing the mobility value up to 450 cm2/V·sec. However, the electrical characteristics for them face the identical trend with temperature heating is degraded. However, the degradation of a-Si:H TFT is worse than that of poly-Si TFT when the device temperature is raised. In this study, the a-Si:H TFTs and poly-Si TFTs with furnace and green laser anneal were chosen. Comparing the transfer characteristics, subthreshold swing (S.S.), threshold voltage (Vth), ON/OFF ratio, field effect mobility (μFE), interface state density (Nit) with temperature effect, some trends are very interesting. The bulk traps were recovered by pseudo-crystallization with increasing temperature, and the transfer characteristics become better than the initial.

Efficiency analysis of electroplating gold bump in assembly

In flat panel displays, the assembly format of driving ICs, due to the rectangular chip shape, is usually with a difference of conventional commercial ICs constructed with a square configuration. Because of this concern, the electroplating gold bump technology in package was desirably developed. Additionally, in the characteristics of hardness, melting point, and stability, gold material is generally better than tin material. Although tin in cost is lower than gold, the previous just can be applied to the soldering joint, but not to the thermal compression process. Therefore, in this study, the electroplating gold bump in assembly was probed in detail to analyze the possibility of mass-production.